Information Management and Interoperability Strategies: The Case for Digital Identifiers. - Robin Wilson (ICWI, 2003)

Temperature Dependence in Low Power CMOS UDSM Process. - B. Lasbouygues; Robin Wilson; Philippe Maurine; Nadine Azémard; Daniel Auvergne (PATMOS, 2004)

Physical Extension of the Logical Effort Model. - B. Lasbouygues; Robin Wilson; Philippe Maurine; Nadine Azémard; Daniel Auvergne (PATMOS, 2004)

Temperature Dependency in UDSM Process. - B. Lasbouygues; Robin Wilson; Nadine Azémard; Philippe Maurine (PATMOS, 2005)

An Open Platform for Developing Multiprocessor SoCs. - Mario Diaz-Nava; Patrick Blouet; Philippe Teninge; Marcello Coppola; Tarek Ben Ismail; Samuel Picchiottino; Robin Wilson (Computer, 2005)

Timing analysis in presence of supply voltage and temperature variations. - B. Lasbouygues; Robin Wilson; Nadine Azémard; Philippe Maurine (ISPD, 2006)

Yield Enhancement Methodology for CMOS Standard Cells. - Arnaud Epinat; N. Vijayaraghavan; Matthieu Sautier; Olivier Callen; Sebastien Fabre; Ryan Ross; Paul Simon; Robin Wilson (ISQED, 2006)

Statistical Characterization of Library Timing Performance. - Vincent Migairou; Robin Wilson; Sylvain Engels; Nadine Azémard; Philippe Maurine (PATMOS, 2006)

Design for Volume Manufacturing in the Deep Submicron ERA. - Robin Wilson (PATMOS, 2006)

A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects. - Sylvain Engels; Robin Wilson; Nadine Azémard; Philippe Maurine (Integr., 2006)

Logical effort model extension to propagation delay representation. - B. Lasbouygues; Sylvain Engels; Robin Wilson; Philippe Maurine; Nadine Azémard; Daniel Auvergne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Temperature and voltage aware timing analysis: application to voltage drops. - B. Lasbouygues; Robin Wilson; Nadine Azémard; Philippe Maurine (DATE, 2007)

A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation. - Vincent Migairou; Robin Wilson; Sylvain Engels; Zeqin Wu; Nadine Azémard; Philippe Maurine (PATMOS, 2007)

Temperature- and Voltage-Aware Timing Analysis. - B. Lasbouygues; Robin Wilson; Nadine Azémard; Philippe Maurine (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Product On-Chip Process Compensation for Low Power and Yield Enhancement. - Nabila Moubdi; Philippe Maurine; Robin Wilson; Nadine Azémard; Vincent Dumettier; Abhishek Bansal 003; Sebastien Barasinski; Alain Tournier; Guy Durieu; David Meyer; Pierre Busson; Sarah Verhaeren; et al. (PATMOS, 2009)

Timing margin evaluation with a simple statistical timing analysis flow. - Vincent Migairou; Robin Wilson; Sylvain Engels; Zeqin Wu; Nadine Azémard; Philippe Maurine (J. Embed. Comput., 2009)

On-Chip Process Variability Monitoring Flow. - Nabila Moubdi; Philippe Maurine; Robin Wilson; Sylvain Engels; Nadine Azémard; Vincent Dumettier; Pierre Busson (J. Low Power Electron., 2010)

Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. - Edith Beigné; Alexandre Valentian; Bastien Giraud; Olivier Thomas; Thomas Benoist; Yvain Thonnart; Serge Bernard; Guillaume Moritz; Olivier Billoint; Y. Maneglia; Philippe Flatresse; Jean-Philippe Noel; et al. (DATE, 2013)

A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC. - Edith Beigné; Ivan Miro-Panades; Yvain Thonnart; Laurent Alacoque; Pascal Vivet; Suzanne Lesecq; Diego Puschini; Farhat Thabet; Benoît Tain; K. Benchehida; Sylvain Engels; Robin Wilson; et al. (ESSCIRC, 2013)

Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology. - Philippe Flatresse; Bastien Giraud; Jean-Philippe Noel; Bertrand Pelloux-Prayer; Fabien Giner; Deepak-Kumar Arora; Franck Arnaud; Nicolas Planes; Julien Le Coz; Olivier Thomas; Sylvain Engels; Giorgio Cesana; et al. (ISSCC, 2013)

Clockless Design Performance Monitoring for Nanometer Technologies. - Marc Renaudin; Aurélien Buhrig; Charles Guillemet; Robin Wilson; Sylvain Engels (ASYNC, 2014)

27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. - Robin Wilson; Edith Beigné; Philippe Flatresse; Alexandre Valentian; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; Anuj Grover; et al. (ISSCC, 2014)

Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI. - Fady Abouzeid; Audrey Bienfait; Kaya Can Akyel; Anis Feki; Sylvain Clerc; Lorenzo Ciampolini; Fabien Giner; Robin Wilson; Philippe Roche (IEEE J. Solid State Circuits, 2014)

A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization. - David Jacquet; Frederic Hasbani; Philippe Flatresse; Robin Wilson; Franck Arnaud; Giorgio Cesana; Thierry Di Gilio; Christophe Lecocq; Tanmoy Roy; Amit Chhabra; Chiranjeev Grover; Olivier Minez; et al. (IEEE J. Solid State Circuits, 2014)

A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC. - Ivan Miro Panades; Edith Beigné; Yvain Thonnart; Laurent Alacoque; Pascal Vivet; Suzanne Lesecq; Diego Puschini; Anca Molnos; Farhat Thabet; Benoît Tain; Karim Ben Chehida; Sylvain Engels; et al. (IEEE J. Solid State Circuits, 2014)

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. - Sylvain Clerc; Fady Abouzeid; Darayus Adil Patel; Jean-Marc Daveau; Cyril Bottoni; Lorenzo Ciampolini; Fabien Giner; David Meyer; Robin Wilson; Philippe Roche; Sylvie Naudet; Arnaud Virazel; et al. (ISQED, 2015)

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. - Edith Beigné; Alexandre Valentian; Ivan Miro Panades; Robin Wilson; Philippe Flatresse; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; et al. (IEEE J. Solid State Circuits, 2015)

Introducing Turing's mathematics. - Robin Whitty; Robin Wilson (The Turing Guide, 2017)

A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI. - Marc Renaudin; Aymane Bouzafour; Sylvain Engels; Robin Wilson (J. Low Power Electron., 2018)

The impact of different slot design of BLDC motor in a complete drive system. - Amit Kumar; Raja Gandhi; Robin Wilson; Rakesh Roy (IECON, 2020)

Working with Lowell. - Robin Wilson (AKCE Int. J. Graphs Comb., 2020)

Circuit Monitoring Across Design Life-Cycle in 28nm FD-SOI and 40nm Bulk CMOS technologies. - Sylvain Clerc; Kedar Janardan Dhori; Robin M. Wilson; Rohit Goel; Sébastien Marchal; Franck Pourchon; Christian Dutto; Ricardo Gomez Gomez (ESSCIRC, 2021)

Effect of Varying Number of Poles on Performance of a PM-Assisted Synchronous Reluctance Machine Enabled with Iron Nitride Magnet Combinations. - Praveen Kumar; Robin Wilson; Ayman M. El-Refaie (IECON, 2023)