On Accuracy of Switch-Level Modeling of Bridging Faults in Complex Gates. - Rochit Rajsuman; Yashwant K. Malaiya; Anura P. Jayasumana (DAC, 1987)

CMOS Stuck-open Fault Detection Using Single Test Patterns. - Rochit Rajsuman; Anura P. Jayasumana; Yashwant K. Malaiya (DAC, 1989)

Limitations of switch level analysis for bridging faults. - Rochit Rajsuman; Yashwant K. Malaiya; Anura P. Jayasumana (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

CMOS stuck-open fault testability. - Rochit Rajsuman; Yashwant K. Malaiya; Anura P. Jayasumana (IEEE J. Solid State Circuits, 1989)

CMOS open-fault detection in the presence of glitches and timing skews. - Rochit Rajsuman; Anura P. Jayasumana; Yashwant K. Malaiya (IEEE J. Solid State Circuits, 1989)

On the testing of microprogrammed processor. - Suntae Hwang; Rochit Rajsuman; Yashwant K. Malaiya (MICRO, 1990)

Implementation of switch network logic in SOI. - Rochit Rajsuman (IEEE J. Solid State Circuits, 1990)

An analysis of feedback bridging faults in MOS VLSI. - Rochit Rajsuman (VTS, 1991)

An analysis and testing of operation induced faults in MOS VLSI. - Rochit Rajsuman; Anura P. Jayasumana; Yashwant K. Malaiya; Juney Park (VTS, 1991)

Design of CMOS circuits for stuck-open fault testability. - Anura P. Jayasumana; Yashwant K. Malaiya; Rochit Rajsuman (IEEE J. Solid State Circuits, 1991)

An analysis and simulation of multiple ring token networks. - David A. Vasko; Rochit Rajsuman (LCN, 1992)

An Architecture To Test Random Access Memories. - Rochit Rajsuman (VLSI Design, 1992)

Coverage of Bridging Faults by Random Testing in IDDQ Test Environment. - Rochit Rajsuman; David A. Penry (VLSI Design, 1993)

IDDQ Detection of CMOS Bridging Faults by Stuck-At Fault Tests. - Suntae Hwang; Rochit Rajsuman; Scott Davidson 001 (VLSI Design, 1994)

A new testing method for EEPLA. - Rochit Rajsuman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Special Issue on Digital Hardware Testing. - Rochit Rajsuman (VLSI Design, 1994)

STD Architecture: A Practical Approach to Test M-Bits Random Access Memories. - Rochit Rajsuman; Kamal Rajkanan (VLSI Design, 1994)

Testable design of BiCMOS circuits for stuck-open fault detection using single patterns. - Sankaran M. Menon; Yashwant K. Malaiya; Anura P. Jayasumana; Rochit Rajsuman (IEEE J. Solid State Circuits, 1995)

Challenge of the 90's: Testing CoreWareTM Based ASICs. - Rochit Rajsuman (ITC, 1996)

VLSI Testing for High Reliability: Mixing IDDQ Testing With Logic Testing. - Suntae Hwang; Rochit Rajsuman (VLSI Design, 1997)

Testing a system-on-a-chip with embedded microprocessor. - Rochit Rajsuman (ITC, 1999)

A new paradigm in test for the next millennium. - Jerry Katz; Rochit Rajsuman (ITC, 2000)

Iddq testing for CMOS VLSI. - Rochit Rajsuman (Proc. IEEE, 2000)

Test and repair of large embedded DRAMs. I. - Roderick McConnell; Rochit Rajsuman; Eric A. Nelson; Jeffrey H. Dreibelbis (ITC, 2001)

Design and Test of Large Embedded Memories: An Overview. - Rochit Rajsuman (IEEE Des. Test Comput., 2001)

Guest Editors' Intoduction: The New World of Large Embedded Memories. - Rochit Rajsuman; Francky Catthoor (IEEE Des. Test Comput., 2001)

Extending EDA Environment From Design to Test. - Rochit Rajsuman (Asian Test Symposium, 2002)

Testing The Tester. - Rochit Rajsuman (ITC, 2002)

Can IC Test Learn from How a Tester is Tested. - Rochit Rajsuman (ITC, 2002)

Guest editorial [Special section on innovations in VLSI automatic test equipment (ATEs)]. - Sunil R. Das; Rochit Rajsuman (IEEE Trans. Instrum. Meas., 2003)

Architecture, design, and application of an event-based test system. - Rochit Rajsuman (IEEE Trans. Instrum. Meas., 2003)

Opportunities with the open architecture test system. - Kazumi Hatayama; Rochit Rajsuman (ASP-DAC, 2004)

New opportunities with the open architecture test system. - Rochit Rajsuman (ASP-DAC, 2004)

An Overview of the Open Architecture Test System. - Rochit Rajsuman (DELTA, 2004)

Open Architecture Test System: System Architecture and Design. - Rochit Rajsuman; Masuda Noriyuki (ITC, 2004)

Guest Editorial First Special Section of the IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT in the Area of VLSI Testing - Future of Semiconductor Test. - Sunil R. Das; Rochit Rajsuman (IEEE Trans. Instrum. Meas., 2005)

Architecture and design of an open ATE to incubate the development of third-party instruments. - Rochit Rajsuman; Masuda Noriyuki; Kazuhiro Yamashita (IEEE Trans. Instrum. Meas., 2005)

Innovation In Test: Where Are We. - Rochit Rajsuman (DELTA, 2006)

Towards The Methodology of On-line Diagnosis. - Rochit Rajsuman (IOLTS, 2006)

Guest Editorial Second Special Section of the IEEE Transactions on Instrumentation and Measurement in the Area of VLSI Testing - Future of Semiconductor Test. - Sunil R. Das; Rochit Rajsuman (IEEE Trans. Instrum. Meas., 2006)