Analysis of single-event upsets in a Microsemi ProAsic3E FPGA. - Paulo Ricardo Cechelero Villa; Roger C. Goerl; Fabian Vargas 001; Leticia B. Poehls; Nilberto H. Medina; Nemitala Added; Vitor A. P. de Aguiar; Eduardo L. A. Macchione; Fernando Aguirre; Marcilei Aparecida Guazzelli da Silveira; Eduardo Augusto Bezerra (LATS, 2017)

An efficient EDAC approach for handling multiple bit upsets in memory array. - Roger C. Goerl; Paulo Ricardo Cechelero Villa; Letícia Maria Veiras Bolzani; Eduardo Augusto Bezerra; Fabian Luis Vargas 001 (Microelectron. Reliab., 2018)

A New Approach to Guarantee Critical Task Schedulability in TDMA-Based Bus Access of Multicore Architecture. - Estevan Lara; Guilherme Debon; Roger C. Goerl; Paulo Ricardo Cechelero Villa; Dorian Schramm; Leticia B. Poehls; Fabian Vargas 001 (LATS, 2019)

Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy. - Paulo Ricardo Cechelero Villa; Rodrigo Travessini; Roger C. Goerl; Fabian Luis Vargas 001; Eduardo Augusto Bezerra (J. Electron. Test., 2019)

Error Coverage, Reliability and Cost Analysis of Fault Tolerance Techniques for 32-bit Memories used on Space Missions. - David C. C. Freitas; David F. M. Mota; Daniel Simões; Clailton Lopes; Roger C. Goerl; César Augusto Missio Marcon; Jarbas A. N. Silveira; João Cesar M. Mota (ISQED, 2020)

Optimizing RISC-V ISA Usage by Sharing Coprocessors on MPSoC. - Pedro Lima; Caio Vieira; Jorge Reis; Alexandre Almeida; Jarbas Silveira; Roger C. Goerl; César A. M. Marcon (LATS, 2020)

PCoSA: A product error correction code for use in memory devices targeting space applications. - David C. C. Freitas; David F. M. Mota; Roger C. Goerl; César A. M. Marcon; Fabian Vargas 001; Jarbas A. N. Silveira; João Cesar M. Mota (Integr., 2020)