Quantitative analysis of vector code. - Roger Espasa; Mateo Valero; David A. Padua; Marta Jiménez; Eduard Ayguadé (PDP, 1995)

Decoupled Vector Architectures. - Roger Espasa; Mateo Valero (HPCA, 1996)

Effective Usage of Vector Registers in Advanced Vector Architectures. - Luís Villa; Roger Espasa; Mateo Valero (IEEE PACT, 1997)

Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance. - Roger Espasa; Mateo Valero (HiPC, 1997)

Multithreaded Vector Architectures. - Roger Espasa; Mateo Valero (HPCA, 1997)

A Victim Cache for Vector Registers. - Roger Espasa; Mateo Valero (International Conference on Supercomputing, 1997)

Out-of-Order Vector Architectures. - Roger Espasa; Mateo Valero; James E. Smith 001 (MICRO, 1997)

Exploiting instruction- and data-level parallelism. - Roger Espasa; Mateo Valero (IEEE Micro, 1997)

Command Vector Memory Systems: High Performance at Low Cost. - Jesús Corbal; Roger Espasa; Mateo Valero (IEEE PACT, 1998)

Vector Architectures: Past, Present and Future. - Roger Espasa; Mateo Valero; James E. Smith 001 (International Conference on Supercomputing, 1998)

A Performance Study of Out-of-order Vector Architectures and Short Registers. - Luís Villa; Roger Espasa; Mateo Valero (International Conference on Supercomputing, 1998)

Dataflow Analysis of Branch Mispredictions and Its Application to Early Resolution of Branch Outcomes. - Alexandre Farcy; Olivier Temam; Roger Espasa; Toni Juan (MICRO, 1998)

A case for merging the ILP and DLP paradigms. - Francisca Quintana; Roger Espasa; Mateo Valero (PDP, 1998)

Effective usage of vector registers in decoupled vector architectures. - Luís Villa; Roger Espasa; Mateo Valero (PDP, 1998)

An ISA Comparison Between Superscalar and Vector Processors. - Francisca Quintana; Roger Espasa; Mateo Valero (VECPAR, 1998)

Registers Size Influence on Vector Architectures. - Luís Villa; Roger Espasa; Mateo Valero (VECPAR, 1998)

Adding a vector unit to a superscalar processor. - Francisca Quintana; Jesús Corbal; Roger Espasa; Mateo Valero (International Conference on Supercomputing, 1999)

Exploiting a New Level of DLP in Multimedia Applications. - Jesús Corbal; Roger Espasa; Mateo Valero (MICRO, 1999)

MOM: a Matrix SIMD Instruction Set Architecture for Multimedia Applications. - Jesús Corbal; Roger Espasa; Mateo Valero (SC, 1999)

A Simulation Study of Decoupled Vector Architectures. - Roger Espasa; Mateo Valero (J. Supercomput., 1999)

On the Efficiency of Reductions in µ-SIMD Media Extensions. - Jesús Corbal; Roger Espasa; Mateo Valero (IEEE PACT, 2001)

Topic 08+13: Instruction-Level Parallelism and Computer Architecture. - Eduard Ayguadé; Fredrik Dahlgren; Christine Eisenbeis; Roger Espasa; Guang R. Gao; Henk L. Muller; Rizos Sakellariou; André Seznec (Euro-Par, 2001)

DLP + TLP Processors for the Next Generation of Media Workloads. - Jesús Corbal; Roger Espasa; Mateo Valero (HPCA, 2001)

Speculative Alias Analysis for Executable Code. - Manel Fernández; Roger Espasa (IEEE PACT, 2002)

Tarantula: A Vector Extension to the Alpha Architecture. - Roger Espasa; Federico Ardanaz; Julio Gago; Roger Gramunt; Isaac Hernandez; Toni Juan; Joel S. Emer; Stephen Felix; P. Geoffrey Lowney; Matthew Mattina; André Seznec (ISCA, 2002)

Three-dimensional memory vectorization for high bandwidth media memory systems. - Jesús Corbal; Roger Espasa; Mateo Valero (MICRO, 2002)

Asim: A Performance Model Framework. - Joel S. Emer; Pritpal S. Ahuja; Eric Borch; Artur Klauser; Chi-Keung Luk; Srilatha Manne; Shubhendu S. Mukherjee; Harish Patil; Steven Wallace; Nathan L. Binkert; Roger Espasa; Toni Juan (Computer, 2002)

Load redundancy elimination on executable code. - Manel Fernández; Roger Espasa; Saumya K. Debray (Concurr. Comput. Pract. Exp., 2003)

A Cost-Effective Architecture for Vectorizable Numerical and Multimedia Applications. - Francisca Quintana; Jesús Corbal; Roger Espasa; Mateo Valero (Theory Comput. Syst., 2003)

Link-Time Optimization Techniques for Eliminating Conditional Branch Redundancies. - Manel Fernández; Roger Espasa (Interaction between Compilers and Computer Architectures, 2004)

Link-Time Path-Sensitive Memory Redundancy Elimination. - Manel Fernández; Roger Espasa (HPCA, 2004)

A Single (Unified) Shader GPU Microarchitecture for Embedded Systems. - Victor Moya Del Barrio; Carlos González; Jordi Roca; Agustín Fernández; Roger Espasa (HiPEAC, 2005)

Shader Performance Analysis on a Modern GPU Architecture. - Victor Moya Del Barrio; Carlos González; Jordi Roca; Agustín Fernández; Roger Espasa (MICRO, 2005)

Conflict-Free Accesses to Strided Vectors on a Banked Cache. - André Seznec; Roger Espasa (IEEE Trans. Computers, 2005)

Workload Characterization of 3D Games. - Jordi Roca; Victor Moya Del Barrio; Carlos González; Chema Solis; Agustín Fernández; Roger Espasa (IISWC, 2006)

ATTILA: a cycle-level execution-driven simulator for modern GPU architectures. - Victor Moya Del Barrio; Carlos González; Jordi Roca; Agustín Fernández; Roger Espasa (ISPASS, 2006)

Larrabee: A Many-Core x86 Architecture for Visual Computing. - Larry Seiler; Doug Carmean; Eric Sprangle; Tom Forsyth; Pradeep Dubey; Stephen Junkins; Adam T. Lake; Robert Cavin; Roger Espasa; Ed Grochowski; Toni Juan; Michael Abrash; et al. (IEEE Micro, 2009)

Larrabee: A Many-Core Intel Architecture for Visual Computing. - Roger Espasa (HiPEAC, 2010)

A SIMD-efficient 14 instruction shader program for high-throughput microtriangle rasterization. - Jordi Roca; Victor Moya Del Barrio; Carlos González; Vicente Escandell; Albert Murciego; Agustín Fernández; Roger Espasa (Vis. Comput., 2010)

Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip. - David R. Ditzel; Roger Espasa; Nivard Aymerich; Allen Baum; Tom Berg; Jim Burr; Eric Hao; Jayesh Iyer; Miquel Izquierdo; Shankar Jayaratnam; Darren Jones; Chris Klingner; et al. (HCS, 2021)