Systolic IIR filters with bit level pipelining. - Roger F. Woods; Simon C. Knowles; John V. McCanny; John G. McWhirter (ICASSP, 1988)

A bit-level systolic architecture for very high performance IIR filters. - Simon C. Knowles; John G. McWhirter; Roger F. Woods; John V. McCanny (ICASSP, 1989)

Bit-Level systolic architectures for high performance IIR filtering. - Simon C. Knowles; John G. McWhirter; Roger F. Woods; John V. McCanny (J. VLSI Signal Process., 1989)

Pipelined two-port adaptor for wave digital filtering. - Rajinder Jit Singh; John V. McCanny; Roger F. Woods (ICASSP, 1990)

Optimized bit level architectures for IIR filtering. - O. C. McNally; John V. McCanny; Roger F. Woods (ICCD, 1990)

A 40 megasample IIR filter chip. - O. C. McNally; John V. McCanny; Roger F. Woods (ASAP, 1991)

Design of a Highly Pipelined 2nd Order IIR Filter Chip. - O. C. McNally; John V. McCanny; Roger F. Woods (VLSI, 1991)

The systematic design of high performance digital filters. - B. P. McGovern; Roger F. Woods; John V. McCanny (ICASSP, 1992)

A high performance IIR filter chip and its evaluation system. - Richard L. Walke; Roger Evans; Roger F. Woods; G. Floyd; K. W. Wood (ASAP, 1994)

A New FFT Architecture and Chip Design for Motion Compensation based on Phase Correlation. - Colin Chiu Wing Hui; Tiong Jiu Ding; John V. McCanny; Roger F. Woods (ASAP, 1996)

VLSI architectures for field programmable gate arrays: a case study. - Roger F. Woods; A. Cassidy; J. Gray (FCCM, 1996)

Architectural Strategies for Implementing an Image Processing Algorithm on XC6000 FPGA. - Jean-Paul Heron; Roger F. Woods (FPL, 1996)

Architectural Synthesis and Efficient Circuit Implementation for Field Programmable Gate Arrays. - David W. Trainor; Roger F. Woods (FPL, 1996)

Error analysis of FFT architectures for digital video applications. - Colin Chiu Wing Hui; Tiong Jiu Ding; John V. McCanny; Roger F. Woods (ICECS, 1996)

A 64-point Fourier transform chip for video motion compensation using phase correlation. - Colin Chiu Wing Hui; Tiong Jiu Ding; John V. McCanny; Roger F. Woods (IEEE J. Solid State Circuits, 1996)

FPGA synthesis on the XC6200 using IRIS and Trianus/Hades (or from heaven to hell and back again). - Roger F. Woods; Stefan H.-M. Ludwig; Jean-Paul Heron; David W. Trainor; Stephan W. Gehring (FCCM, 1997)

Architectural Synthesis of Digital Signal Processing Algorithms Using "IRIS". - David W. Trainor; Roger F. Woods; John V. McCanny (J. VLSI Signal Process., 1997)

The impact of data characteristics on hardware selection for low-power DSP. - Gareth Keane; Jonathan R. Spanier; Roger F. Woods (EUSIPCO, 1998)

Fast Partial Reconfiguration for FCCMs. - Sakir Sezer; Roger F. Woods; Jean-Paul Heron; Alan Marshall 001 (FCCM, 1998)

The impact of data characteristics and hardware topology on hardware selection for low power DSP. - Gareth Keane; Jonathan R. Spanier; Roger F. Woods (ISLPED, 1998)

Applying an XC6200 to Real-Time Image Processing. - Roger F. Woods; David W. Trainor; Jean-Paul Heron (IEEE Des. Test Comput., 1998)

Accelerating Run-Time Reconfiguration on FCCMs. - Jean-Paul Heron; Roger F. Woods (FCCM, 1999)

A Virtual Hardware Handler for RTR Systems. - Richard H. Turner; Roger F. Woods; Sakir Sezer; Jean-Paul Heron (FCCM, 1999)

Novel mapping of a linear QR architecture. - Gaye Lightbody; Richard L. Walke; Roger F. Woods; John V. McCanny (ICASSP, 1999)

Tracking performance of momentum LMS algorithm for a chirped sinusoidal signal. - Lok-Kee Ting; C. F. N. Cowan; Roger F. Woods (EUSIPCO, 2000)

An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing. - Tim Courtney; Richard H. Turner; Roger F. Woods (FCCM, 2000)

Multiplexer Based Reconfiguration for Virtex Multipliers. - Tim Courtney; Richard H. Turner; Roger F. Woods (FPL, 2000)

Linear QR Architecture for a Single Chip Adaptive Beamformer. - Gaye Lightbody; Richard L. Walke; Roger F. Woods; John V. McCanny (J. VLSI Signal Process., 2000)

Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver. - Lok-Kee Ting; Roger F. Woods; Colin Cowan (FPL, 2001)

Implementation of fixed DSP functions using the reduced coefficient multiplier. - Richard H. Turner; Tim Courtney; Roger F. Woods (ICASSP, 2001)

Advances in adaptive signal processing: totally adaptive systems. - Colin Cowan; Roger F. Woods; Jean-Paul Heron; P. Power; F. J. Sweeney (Annu. Rev. Control., 2001)

Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead. - Jean-Paul Heron; Roger F. Woods; Sakir Sezer; Richard H. Turner (J. VLSI Signal Process., 2001)

Mapping Multi-Mode Circuits to LUT-Based FPGA Using Embedded MUXes. - Tim Courtney; Richard H. Turner; Roger F. Woods (FCCM, 2002)

Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs. - Richard H. Turner; Roger F. Woods; Tim Courtney (FPL, 2002)

FPGA-based system-level design framework based on the IRIS synthesis tool and System Generator. - Ying Yi; Roger F. Woods (FPT, 2002)

Design Flow for Efficient FPGA Reconfiguration. - Richard H. Turner; Roger F. Woods (FPL, 2003)

Design of a parameterizable silicon intellectual property core for QR-based RLS filtering. - Gaye Lightbody; Roger F. Woods; Richard L. Walke (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Embedded Context Aware Hardware Component Generation for Dataflow System Exploration. - John McAllister; Roger F. Woods; Richard L. Walke (SAMOS, 2004)

LMS coefficient filtering for Time-varying chirped signals. - Lok-Kee Ting; Colin F. N. Cowan; Roger F. Woods (IEEE Trans. Signal Process., 2004)

Highly efficient, limited range multipliers for LUT-based FPGA architectures. - Richard H. Turner; Roger F. Woods (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Guest Editorial: Field Programmable Logic. - Roger F. Woods; Russell Tessier (J. VLSI Signal Process., 2004)

Parallel implementation of finite difference schemes for the plate equation on a FPGA-based multi-processor array. - Erdem Motuk; Roger F. Woods; Stefan Bilbao (EUSIPCO, 2005)

FPGA Core Network Implementation and Optimization: A Case Study. - Scott Fischaber; R. Hasson; John McAllister; Roger F. Woods (FPT, 2005)

FPGA-Based Hardware for Physical Modelling Sound Synthesis by Finite Difference Schemes. - Erdem Motuk; Roger F. Woods; Stefan Bilbao (FPT, 2005)

Implementation of finite difference schemes for the wave equation on FPGA. - Erdem Motuk; Roger F. Woods; Stefan Bilbao (ICASSP (3), 2005)

Rapid generation of hardware functionality in heterogeneous platforms [FPGA implementation applications]. - Darren Gerard Reilly; Roger F. Woods; John McAllister; Richard L. Walke (ICASSP (5), 2005)

Programmable Network Functionality for Improved QoS of Interactive Video Traffic. - Brendan McAllister; Alan Marshall 001; Roger F. Woods (Net-Con, 2005)

A Novel Packet Marking Function for Real-Time Interactive MPEG-4 Video Applications in a Differentiated Services Network. - Shane O'Neill; Alan Marshall 001; Roger F. Woods (NETWORKING, 2005)

Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms. - John McAllister; Roger F. Woods; Darren Gerard Reilly; Scott Fischaber; R. Hasson (SAMOS, 2005)

Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers. - Lok-Kee Ting; Roger F. Woods; C. F. N. Cowan (IEEE Trans. Very Large Scale Integr. Syst., 2005)

High Speed FPGA-Based Implementations of Delayed-LMS Filters. - Ying Yi; Roger F. Woods; Lok-Kee Ting; C. F. N. Cowan (J. VLSI Signal Process., 2005)

Muir Hardware Synthesis for Multimedia Applications. - Scott Fischaber; John McAllister; Roger F. Woods; E. Malins (ESTIMedia, 2006)

Providing Input-Output Throughput Guarantees in a Buffered Crossbar Switch. - Shane O'Neill; Alan Marshall 001; Roger F. Woods (ISCC, 2006)

Hierarchical synthesis of complex DSP functions using IRIS. - Ying Yi; Roger F. Woods (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Multidimensional DSP Core Synthesis for FPGA. - John McAllister; Roger F. Woods; Richard L. Walke; Darren Gerard Reilly (J. VLSI Signal Process., 2006)

Soft IP core implementation of recursive least squares filter using only multplicative and additive operators. - Gaye Lightbody; Roger F. Woods; Jonathan Francey (FPL, 2007)

Physical Models and Musical Controllers - Designing a Novel Electronic Percussion Instrument. - Katarzyna Chuchacz; Sile O'Modhrain; Roger F. Woods (NIME, 2007)

Transforming Signal Processing Applications into Parallel Implementations. - Ed F. Deprettere; Roger F. Woods; Ingrid Verbauwhede; Erwin A. de Kock (EURASIP J. Adv. Signal Process., 2007)

Rapid implementation and optimisation of DSP systems on FPGA-centric heterogeneous platforms. - John McAllister; Roger F. Woods; Scott Fischaber; E. Malins (J. Syst. Archit., 2007)

Design Methodology for Real-Time FPGA-Based Sound Synthesis. - Erdem Motuk; Roger F. Woods; Stefan Bilbao; John McAllister (IEEE Trans. Signal Process., 2007)

QR Recursive Least Squares IP Core Example. - Gaye Lightbody; Roger F. Woods (ECBS, 2008)

Power efficient DSP datapath configuration methodology for FPGA. - Stephen McKeown; Roger F. Woods; John McAllister (FPL, 2008)

Novel percussive Instrument Design - Converting Mathematical Formulae into engaging Musical Instruments. - Katarzyna Chuchacz; Roger F. Woods; Sile O'Modhrain (ICMC, 2008)

Combining noise compensation and missing-feature decoding for large vocabulary speech recognition in noise. - Jianhua Lu; Ji Ming; Roger F. Woods (INTERSPEECH, 2008)

A real-time flow monitor architecture encompassing on-demand monitoring functions. - John McGlone; Alan Marshall 001; Roger F. Woods (NOMS, 2008)

Memory-Centric Hardware Synthesis from Dataflow Models. - Scott Fischaber; John McAllister; Roger F. Woods (SAMOS, 2008)

Power efficient dynamic-range utilisation for DSP on FPGA. - Stephen McKeown; Roger F. Woods; John McAllister (SiPS, 2008)

Current Trends on Reconfigurable Computing. - Jürgen Becker 001; Michael Hübner 001; Roger F. Woods; Philip Heng Wai Leong; Robert Esser; Lionel Torres (Int. J. Reconfigurable Comput., 2008)

From Bit Level Systolic Arrays to HDTV Processor Chips. - Roger F. Woods; John V. McCanny; John G. McWhirter (J. Signal Process. Syst., 2008)

An Attack-Resilent Sampling Mechanism for Integrated IP Flow Monitors. - John McGlone; Alan Marshall 001; Roger F. Woods (ICDCS Workshops, 2009)

A traffic manager for integrated queuing and scheduling of unicast and multicast IP traffic. - Qi Zhang 026; Alan Marshall 001; Roger F. Woods (ICT, 2009)

Replacing uncertainty decoding with subband re-estimation for large vocabulary speech recognition in noise. - Jianhua Lu; Ji Ming; Roger F. Woods (INTERSPEECH, 2009)

Introduction to the Special Issue ARC'08. - Katherine Compton; Roger F. Woods; Christos-Savvas Bouganis; Pedro C. Diniz (ACM Trans. Reconfigurable Technol. Syst., 2009)

Mapping Decidable Signal Processing Graphs into FPGA Implementations. - Roger F. Woods (Handbook of Signal Processing Systems, 2010)

Random clock against differential power analysis. - Keanhong Boey; Yingxi Lu; Máire O'Neill; Roger F. Woods (APCCAS, 2010)

Adapting noisy speech models - Extended uncertainty decoding. - Jianhua Lu; Ji Ming; Roger F. Woods (ICASSP, 2010)

Security of AES Sbox designs to power analysis. - Keanhong Boey; Philip Hodgers; Yingxi Lu; Máire O'Neill; Roger F. Woods (ICECS, 2010)

Differential Power Analysis of CAST-128. - Keanhong Boey; Yingxi Lu; Máire O'Neill; Roger F. Woods (ISVLSI, 2010)

Design of a flexible high-speed FPGA-based flow monitor for next generation networks. - John McGlone; Roger F. Woods; Alan Marshall 001; Michaela Blott (ICSAMOS, 2010)

A Programmable Architecture for Layered Multimedia Streams in IPv6 Networks. - Brendan McAllister; Alan Marshall 001; Roger F. Woods (J. Networks, 2010)

Guest Editorial ARC 2009. - Roger F. Woods; Jürgen Becker 001; Peter Athanas; Fearghal Morgan (ACM Trans. Reconfigurable Technol. Syst., 2010)

SoC Memory Hierarchy Derivation from Dataflow Graphs. - Scott Fischaber; Roger F. Woods; John McAllister (J. Signal Process. Syst., 2010)

Session MA8b1: Computer arithmetic I. - Roger F. Woods (ACSCC, 2011)

Design and implementation of a flexible Queue Manager for Next Generation Networks. - Qi Zhang 026; Roger F. Woods; Alan Marshall 001 (ACSCC, 2011)

A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM Detection. - Xuezheng Chu; John McAllister; Roger F. Woods (ARC, 2011)

How Resistant are Sboxes to Power Analysis Attacks? - Keanhong Boey; Máire O'Neill; Roger F. Woods (NTMS, 2011)

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality. - Stephen McKeown; Roger F. Woods (IET Comput. Digit. Tech., 2011)

FPGA Implementation of a Pipelined Gaussian Calculation for HMM-Based Large Vocabulary Speech Recognition. - Richard Veitch; Louis-Marie Aubert; Roger F. Woods; Scott Fischaber (Int. J. Reconfigurable Comput., 2011)

A Scalable and Programmable Modular Traffic Manager Architecture. - Shane O'Neill; Roger F. Woods; Alan Marshall 001; Qi Zhang 026 (ACM Trans. Reconfigurable Technol. Syst., 2011)

Real-Valued Fixed-Complexity Sphere Decoder for High Dimensional QAM-MIMO Systems. - C. Zheng; Xuezheng Chu; John McAllister; Roger F. Woods (IEEE Trans. Signal Process., 2011)

Session TA5b: Computer arithmetic accelerators for signal processing. - Roger F. Woods (ACSCC, 2012)

Novel Application of Genetic Sequencing Algorithms to Optimization of Hardware Resource Sharing for DSP. - Stephen McKeown; Roger F. Woods (ASAP, 2012)

Preface - ARC. - Andreas Koch 001; Roger F. Woods (Microprocess. Microsystems, 2012)

An On-Demand Queue Management Architecture for a Programmable Traffic Manager. - Qi Zhang 026; Roger F. Woods; Alan Marshall 001 (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Implementation of selective packet destruction on wireless open-access research platform. - S. Hughes; B. Zhou; Roger F. Woods; Alan Marshall 001 (ACSSC, 2013)

Optimization of Weighted Finite State Transducer for Speech Recognition. - Louis-Marie Aubert; Roger F. Woods; Scott Fischaber; Richard Veitch (IEEE Trans. Computers, 2013)

Power Efficient, FPGA Implementations of Transform Algorithms for Radar-Based Digital Receiver Applications. - Stephen McKeown; Roger F. Woods (IEEE Trans. Ind. Informatics, 2013)

Mapping Decidable Signal Processing Graphs into FPGA Implementations. - Roger F. Woods (Handbook of Signal Processing Systems, 2013)

Dataflow toolset for soft-core processors on FPGA for image processing applications. - Burak Bardak; Fahad Manzoor Siddiqui; Colm Kelly; Roger F. Woods (ACSSC, 2014)

Investigation of secure wireless regions using configurable beamforming on WARP. - Yuanrui Zhang; Bei Yin; Roger F. Woods; Joseph R. Cavallaro; Alan Marshall 001; Youngwook Ko (ACSSC, 2014)

Power modelling and capping for heterogeneous ARM/FPGA SoCs. - Yun Wu 003; José L. Núñez-Yáñez; Roger F. Woods; Dimitrios S. Nikolopoulos (FPT, 2014)

Secure key generation from OFDM subcarriers' channel responses. - Junqing Zhang; Alan Marshall 001; Roger F. Woods; Trung Quang Duong (GLOBECOM Workshops, 2014)

Creating secure wireless regions using configurable beamforming. - Yuanrui Zhang; Alan Marshall 001; Roger F. Woods; Youngwook Ko (PIMRC, 2014)

Histogram of oriented gradients front end processing: An FPGA based processor approach. - Colm Kelly; Fahad Manzoor Siddiqui; Burak Bardak; Roger F. Woods (SiPS, 2014)

IPPro: FPGA based image processing processor. - Fahad Manzoor Siddiqui; Matthew Russell; Burak Bardak; Roger F. Woods; Karen Rafferty (SiPS, 2014)

Verification of Key Generation from Individual OFDM Subcarrier's Channel Response. - Junqing Zhang; Roger F. Woods; Alan Marshall 001; Trung Quang Duong (GLOBECOM Workshops, 2015)

An effective key generation system using improved channel reciprocity. - Junqing Zhang; Roger F. Woods; Alan Marshall 001; Trung Quang Duong (ICASSP, 2015)

On spatial security outage probability derivation of exposure region based beamforming with randomly located eavesdroppers. - Yuanrui Zhang; Youngwook Ko; Roger F. Woods; Alan Marshall 001; Joe Cavallaro; Kaipeng Li (ACSSC, 2016)

FPGA Soft-Core Processors, Compiler and Hardware Optimizations Validated Using HOG. - Colm Kelly; Fahad Manzoor Siddiqui; Burak Bardak; Yun Wu 003; Roger F. Woods; Karen Rafferty (ARC, 2016)

Proposing the Deep Dynamic Bayesian Network as a Future Computer Based Medical System. - Caoimhe M. Carbery; Adele H. Marshall; Roger F. Woods (CBMS, 2016)

NanoStreams: Codesigned microservers for edge analytics in real time. - Giorgis Georgakoudis; Charles Gillan; Ahmad Hassan; Umar Ibrahim Minhas; Ivor T. A. Spence; George Tzenakis; Hans Vandierendonck; Roger F. Woods; Dimitrios S. Nikolopoulos; Murali Shyamsundar; Paul Barber; Matthew Russell; et al. (SAMOS, 2016)

Runtime support for adaptive power capping on heterogeneous SoCs. - Yun Wu 003; Dimitrios S. Nikolopoulos; Roger F. Woods (SAMOS, 2016)

Experimental study on channel reciprocity in wireless key generation. - Junqing Zhang; Roger F. Woods; Trung Quang Duong; Alan Marshall 001; Yuan Ding 001 (SPAWC, 2016)

Key Generation From Wireless Channels: A Review. - Junqing Zhang; Trung Quang Duong; Alan Marshall 001; Roger F. Woods (IEEE Access, 2016)

Experimental Study on Key Generation for Physical Layer Security in Wireless Communications. - Junqing Zhang; Roger F. Woods; Trung Quang Duong; Alan Marshall 001; Yuan Ding 001; Yi Huang 001; Qian Xu 012 (IEEE Access, 2016)

Defining Spatial Security Outage Probability for Exposure Region Based Beamforming. - Yuanrui Zhang; Youngwook Ko; Roger F. Woods; Alan Marshall 001 (CoRR, 2016)

Efficient Key Generation by Exploiting Randomness From Channel Responses of Individual OFDM Subcarriers. - Junqing Zhang; Alan Marshall 001; Roger F. Woods; Trung Quang Duong (IEEE Trans. Commun., 2016)

Securing Wireless Communications of the Internet of Things from the Physical Layer, An Overview. - Junqing Zhang; Trung Quang Duong; Roger F. Woods; Alan Marshall 001 (Entropy, 2017)

On the Key Generation From Correlated Wireless Channels. - Junqing Zhang; Biao He; Trung Quang Duong; Roger F. Woods (IEEE Commun. Lett., 2017)

Design of an OFDM Physical Layer Encryption Scheme. - Junqing Zhang; Alan Marshall 001; Roger F. Woods; Trung Quang Duong (IEEE Trans. Veh. Technol., 2017)

Defining Spatial Secrecy Outage Probability for Exposure Region-Based Beamforming. - Yuanrui Zhang; Youngwook Ko; Roger F. Woods; Alan Marshall 001 (IEEE Trans. Wirel. Commun., 2017)

FPGA-Based Soft-Core Processors for Image Processing Applications. - Moslem Amiri; Fahad Manzoor Siddiqui; Colm Kelly; Roger F. Woods; Karen Rafferty; Burak Bardak (J. Signal Process. Syst., 2017)

Exploring Functional Acceleration of OpenCL on FPGAs and GPUs Through Platform-Independent Optimizations. - Umar Ibrahim Minhas; Roger F. Woods; George Karakonstantis (ARC, 2018)

Facilitating Easier Access to FPGAs in the Heterogeneous Cloud Ecosystems. - Umar Ibrahim Minhas; Roger F. Woods; Georgios Karakonstantis (FPL, 2018)

A Bayesian network based learning system for modelling faults in large-scale manufacturing. - Caoimhe M. Carbery; Roger F. Woods; Adele H. Marshall (ICIT, 2018)

Opportunistic Non-Orthogonal Multiple Access Scheme with Unreliable Wireless Backhauls. - Sunyoung Lee; Trung Quang Duong; Roger F. Woods (PIMRC, 2018)

Security Optimization of Exposure Region-Based Beamforming With a Uniform Circular Array. - Yuanrui Zhang; Roger F. Woods; Youngwook Ko; Alan Marshall 001; Junqing Zhang (IEEE Trans. Commun., 2018)

NanoStreams: A Microserver Architecture for Real-Time Analytics on Fast Data Streams. - Umar Ibrahim Minhas; Matthew Russell; Stelios Kaloutsakis; Paul Barber; Roger F. Woods; Giorgis Georgakoudis; Charles Gillan; Dimitrios S. Nikolopoulos; Angelos Bilas (IEEE Trans. Multi Scale Comput. Syst., 2018)

Evaluation of FPGA Partitioning Schemes for Time and Space Sharing of Heterogeneous Tasks. - Umar Ibrahim Minhas; Roger F. Woods; Georgios Karakonstantis (ARC, 2019)

Design space exploration of multi-task processing on space shared FPGAs: work-in-progress. - Umar Ibrahim Minhas; Roger F. Woods; Georgios Karakonstantis (CODES+ISSS, 2019)

Optimisation of System Throughput Exploiting Tasks Heterogeneity on Space Shared FPGAs. - Umar Ibrahim Minhas; Roger F. Woods; Georgios Karakonstantis (FPT, 2019)

FPGA-Based Processor Acceleration for Image Processing Applications. - Fahad Manzoor Siddiqui; Sam Amiri; Umar Ibrahim Minhas; Tiantai Deng; Roger F. Woods; Karen Rafferty; Daniel Crookes (J. Imaging, 2019)

An Investigation of Using Loop-Back Mechanism for Channel Reciprocity Enhancement in Secret Key Generation. - Linning Peng; Guyue Li; Junqing Zhang; Roger F. Woods; Ming Liu 010; Aiqun Hu (IEEE Trans. Mob. Comput., 2019)

Impact of Wireless Backhaul Unreliability and Imperfect Channel Estimation on Opportunistic NOMA. - Sunyoung Lee; Trung Q. Duong; Roger F. Woods (IEEE Trans. Veh. Technol., 2019)

Physical Layer Security for the Internet of Things: Authentication and Key Generation. - Junqing Zhang; Sekhar Rajendran; Zhi Sun; Roger F. Woods; Lajos Hanzo (IEEE Wirel. Commun., 2019)

TOD: Transprecise Object Detection to Maximise Real-Time Accuracy on the Edge. - JunKyu Lee; Blesson Varghese; Roger F. Woods; Hans Vandierendonck (ICFEC, 2021)

Leveraging Transprecision Computing for Machine Vision Applications at the Edge. - Umar Ibrahim Minhas; Lev Mukhanov; Georgios Karakonstantis; Hans Vandierendonck; Roger F. Woods (SiPS, 2021)

Radio Frequency Fingerprint Identification for Narrowband Systems, Modelling and Classification. - Junqing Zhang; Roger F. Woods; Magnus Sandell; Mikko Valkama; Alan Marshall 001; Joseph R. Cavallaro (IEEE Trans. Inf. Forensics Secur., 2021)

Evaluation of Static Mapping for Dynamic Space-Shared Multi-task Processing on FPGAs. - Umar Ibrahim Minhas; Roger F. Woods; Georgios Karakonstantis (J. Signal Process. Syst., 2021)

Multi-spectral In-Vivo FPGA-Based Surgical Imaging. - Majed Alsharari; Lorenzo Niemitz; Simon Sorensen; Roger F. Woods; Ray Burke; Stefan Andersson-Engels; Carlos Reaño; Son T. Mai (ARC, 2022)

A Soft Coprocessor Approach for Developing Image and Video Processing Applications on FPGAs. - Tiantai Deng; Danny Crookes; Roger F. Woods; Fahad Manzoor Siddiqui (J. Imaging, 2022)

Detecting Vehicle Loading Events in Bridge Rotation Data Measured with Multi-Axial Accelerometers. - Alan J. Ferguson; Roger F. Woods; David Hester (Sensors, 2022)

Efficient, Dynamic Multi-Task Execution on FPGA-Based Computing Systems. - Umar Ibrahim Minhas; Roger F. Woods; Dimitrios S. Nikolopoulos; Georgios Karakonstantis (IEEE Trans. Parallel Distributed Syst., 2022)

Increased Leverage of Transprecision Computing for Machine Vision Applications at the Edge. - Umar Ibrahim Minhas; JunKyu Lee; Lev Mukhanov; Georgios Karakonstantis; Hans Vandierendonck; Roger F. Woods (J. Signal Process. Syst., 2022)

An Intelligent Image Processing System for Enhancing Blood Vessel Segmentation on Low-Power SoC. - Majed Alsharari; Son T. Mai; Romain Garnier; Carlos Reaño; Roger F. Woods (SAMOS, 2023)

ENAP: An Efficient Number-Aware Pruning Framework for Design Space Exploration of Approximate Configurations. - Yuqin Dou; Chenghua Wang; Roger F. Woods; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Systematic Approach to Filter Specification for Measuring Quasi-Static Bridge Rotation Under Moving Loads Using DC Accelerometers. - Alan J. Ferguson; David Hester; Roger F. Woods (IEEE Access, 2024)

Adaptive approximate computing in edge AI and IoT applications: A review. - Hans Jakob Damsgaard; Antoine Grenier; Dewant Katare; Zain Taufique; Salar Shakibhamedan; Tiago Troccoli; Georgios Chatzitsompanis; Anil Kanduri; Aleksandr Ometov; Aaron Yi Ding; Nima Taherinejad; Georgios Karakonstantis; et al. (J. Syst. Archit., 2024)

FPAX: A Fast Prior Knowledge-Based Framework for DSE in Approximate Configurations. - Yuqin Dou; Chenghua Wang; Haroon Waris; Roger F. Woods; Weiqiang Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

CACTUS: A Comprehensive Abstraction and Classification Tool for Uncovering Structures. - Luca Gherardini; Varun Ravi Varma; Karol Capala; Roger F. Woods; José L. R. Sousa (ACM Trans. Intell. Syst. Technol., 2024)

Towards Receiver-Agnostic and Collaborative Radio Frequency Fingerprint Identification. - Guanxiong Shen; Junqing Zhang; Alan Marshall 001; Roger F. Woods; Joseph R. Cavallaro; Liquan Chen (IEEE Trans. Mob. Comput., 2024)

Randomised sketching of parametric linear systems. - Nick Polydorides; Hamid Noori; Hans Vandierendonck; Roger F. Woods (SSP, 2025)

Efficient Integer-Only-Inference of Gradient Boosting Decision Trees on Low-Power Devices. - Majed Alsharari; Son T. Mai; Roger F. Woods; Carlos Reaño (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Novel Error Metric for Evaluating the Error Correction Capability of Approximate Units. - Yuqin Dou; Zhikuang Cai; Haroon Waris; Roger F. Woods; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)