A 70-mu m Pitch 8-mu W Self-Biased Charge-Integration Active Pixel for Digital Mammography. - Roger Figueras; Justo Sabadell; Lluís Terés; Francisco Serra-Graells (IEEE Trans. Biomed. Circuits Syst., 2011)

Highly linear integrate-and-fire modulators with soft reset for low-power high-speed imagers. - Michele Dei; Roger Figueras; Josep Maria Margarit; Lluís Terés; Francisco Serra-Graells (ISCAS, 2017)

A 128× 128-pix 4-kfps 14-bit Digital-Pixel PbSe-CMOS Uncooled MWIR Imager. - Roger Figueras; Josep Maria Margarit; German Vergara; Victor Villamayor; Raúl Gutiérrez-Álvarez; Carlos Fernández-Montojo; Lluís Terés; Francisco Serra-Graells (ISCAS, 2018)

An Academic RISC-V Silicon Implementation Based on Open-Source Components. - Jaume Abella 001; Calvin Bulla; Guillem Cabo; Francisco J. Cazorla; Adrián Cristal; Max Doblas; Roger Figueras; Alberto González 004; Carles Hernández 001; César Hernández; Víctor Jiménez; Leonidas Kosmidis; et al. (DCIS, 2020)

BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge. - Enrico Reggiani; Cristóbal Ramírez Lazo; Roger Figueras Bagué; Adrián Cristal; Mauro Olivieri; Osman Sabri Unsal (ASPLOS, 2022)

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. - Guillem Cabo; Gerard Candón; Xavier Carril; Max Doblas; Marc Domínguez; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2022)

Adaptable Register File Organization for Vector Processors. - Cristóbal Ramírez Lazo; Enrico Reggiani; Carlos Rojas Morales; Roger Figueras Bagué; Luis A. Villa Vargas; Marco Antonio Ramírez Salinas; Mateo Valero Cortés; Osman Sabri Unsal; Adrián Cristal (HPCA, 2022)

Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology. - Max Doblas; Gerard Candón; Xavier Carril; Marc Domínguez; Enric Erra; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2023)

VAQUERO: A Scratchpad-based Vector Accelerator for Query Processing. - Julián Pavón; Iván Vargas Valdivieso; Joan Marimon; Roger Figueras; Francesc Moll; Osman S. Unsal; Mateo Valero; Adrián Cristal (HPCA, 2023)

WFAsic: A High-Performance ASIC Accelerator for DNA Sequence Alignment on a RISC-V SoC. - Abbas Haghi; Lluc Alvarez; Jordi Fornt; Juan Miguel De Haro Ruiz; Roger Figueras; Max Doblas; Santiago Marco-Sola; Miquel Moretó (ICPP, 2023)

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications. - Francesco Minervini; Oscar Palomar; Osman S. Unsal; Enrico Reggiani; Josue V. Quiroga; Joan Marimon; Carlos Rojas; Roger Figueras; Abraham Ruiz; Alberto González 004; Jonnatan Mendoza; Iván Vargas; et al. (ACM Trans. Archit. Code Optim., 2023)

QUETZAL: Vector Acceleration Framework for Modern Genome Sequence Analysis Algorithms. - Julian Pavon; Iván Vargas Valdivieso; Carlos Rojas; César Hernández; Mehmet Aslan; Roger Figueras; Yichao Yuan; Joël Lindegger; Mohammed Alser; Francesc Moll; Santiago Marco-Sola; Oguz Ergin; et al. (ISCA, 2024)

Empowering Vector Architectures for ML: The CAMP Architecture for Matrix Multiplication. - Mohammadreza Esmali Nojehdeh; Hossein Mokhtarnia; Julian Pavon Rivera; Narcis Rodas Quiroga; Roger Figueras Bagué; Enrico Reggiani; Miquel Moretó; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé (CoRR, 2025)