Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET. - Shimpei Yamaguchi; Liesbeth Witters; Jérôme Mitard; Geert Eneman; Geert Hellings; Andriy Hikavyy; Roger Loo; Naoto Horiguchi (Microelectron. Reliab., 2018)

60Gb/s waveguide-coupled O-band GeSi quantum-confined Stark effect electro-absorption modulator. - Srinivasan Ashwyn Srinivasan; Clement Porret; Sadhishkumar Balakrishnan; Yoojin Ban; Roger Loo; Peter Verheyen; Joris Van Campenhout; Marianna Pantouvaki (OFC, 2021)

Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections. - A. Vandooren; N. Parihar; Jacopo Franco; Roger Loo; Hiroaki Arimura; R. Rodriguez; F. Sebaai; S. Iacovo; Kevin Vandersmissen; W. Li; G. Mannaert; D. Radisic; et al. (VLSI Technology and Circuits, 2022)

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. - Anabela Veloso; Anne Jourdain; D. Radisic; Rongmei Chen; G. Arutchelvan; B. O'Sullivan; Hiroaki Arimura; Michele Stucchi; An De Keersgieter; M. Hosseini; T. Hopf; K. D'Have; et al. (VLSI Technology and Circuits, 2022)

NPN Si/SiGe memory selector with non-linearity>105 and ON-current>6MA/cm2. - Gaspard Hiblot; Taras Ravsher; Roger Loo; Bhuvaneshwari Yengula Venkata Ramana; Nathali Franchina-Vergel; Andrea Fantini; Shamin Houshmand Sharifi; Nina Bazzazian; Kurt Wostyn; Loris Angelo Labbate; Sebastien Couet; Gouri Sankar Kar (ESSDERC, 2023)

Comprehensive 300 mm process for Silicon spin qubits with modular integration. - A. Elsayed; Clement Godfrin; Nard I. Dumoulin Stuyck; M. M. K. Shehata; Stefan Kubicek; S. Massar; Yann Canvel; Julien Jussot; Andriy Hikavyy; Roger Loo; George Simion; Massimo Mongillo; et al. (VLSI Technology and Circuits, 2023)

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning. - Hans Mertens; M. Hosseini; Thomas Chiarella; D. Zhou; S. Wang; G. Mannaert; E. Dupuy; D. Radisic; Z. Tao; Yusuke Oniki; Andriy Hikavyy; R. Rosseel; et al. (VLSI Technology and Circuits, 2023)

Monolithic Complementary Field Effect Transistors (CFET) Demonstrated using Middle Dielectric Isolation and Stacked Contacts. - Steven Demuynck; Victor Vega-Gonzalez; C. Toledo de Carvalho Cavalcante; L. Petersen Barbosa Lima; K. Stiers; C. Sheng; A. Vandooren; M. Hosseini; X. Zhou; Hans Mertens; Thomas Chiarella; Jürgen Bömmels; et al. (VLSI Technology and Circuits, 2024)