A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibration. - Rohan Sehgal; Frank M. L. van der Goes; Klaas Bult (ESSCIRC, 2014)

A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction. - Md Shakil Akter; Rohan Sehgal; Frank M. L. van der Goes; Klaas Bult (ESSCIRC, 2015)

A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration. - Rohan Sehgal; Frank M. L. van der Goes; Klaas Bult (IEEE J. Solid State Circuits, 2015)

A 13mW 64dB SNDR 280MS/s pipelined ADC using linearized open-loop class-AB amplifiers. - Rohan Sehgal; Frank M. L. van der Goes; Klaas Bult (ESSCIRC, 2017)

A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier. - Md Shakil Akter; Rohan Sehgal; Frank M. L. van der Goes; Kofi A. A. Makinwa; Klaas Bult (IEEE J. Solid State Circuits, 2018)

A 13-mW 64-dB SNDR 280-MS/s Pipelined ADC Using Linearized Integrating Amplifiers. - Rohan Sehgal; Frank M. L. van der Goes; Klaas Bult (IEEE J. Solid State Circuits, 2018)

A Resistive Degeneration Technique for Linearizing Open-Loop Amplifiers. - Md Shakil Akter; Rohan Sehgal; Klaas Bult (IEEE Trans. Circuits Syst., 2020)