A New Divide and Conquer Method for Achieving High Speed Division in Hardware. - Murali Mohan; Rohini Krishnan; Anshul Kumar; M. Balakrishnan (ASP-DAC/VLSI Design, 2002)

Encoded-Low Swing Technique for Ultra Low Power Interconnect. - Rohini Krishnan; José Pineda de Gyvez; Harry J. M. Veendrick (FPL, 2003)

Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks. - Rohini Krishnan; Om Prakash Gangwal; Jos T. J. van Eijndhoven; Anshul Kumar (VLSI Design, 2003)

Low energy FPGA interconnect design. - Rohini Krishnan; José Pineda de Gyvez; Martijn T. Bennebroek (FPGA, 2004)

Low Energy Switch Block For FPGAs. - Rohini Krishnan; José Pineda de Gyvez (VLSI Design, 2004)

Energy-efficient FPGA interconnect architecture design (abstract only). - Rohini Krishnan; R. I. M. P. Meijer; Durand Guillaume (FPGA, 2005)

Energy-efficient FPGA interconnect design. - Maurice Meijer; Rohini Krishnan; Martijn T. Bennebroek (DATE Designers' Forum, 2006)

Design techniques for reference clock jitter optimization for high speed PHYs. - Rohini Krishnan; Tejas P. Potphode; Ashish Sharma 009; Haijin Zhang; Herry Hu; David R. Mulvihill (DTTIS, 2023)

2.3 Granite Rapids-D: Intel Xeon 6 SoC for vRAN, Edge, Networking, and Storage. - Raj R. Varada; Rohini Krishnan; Ajith Subramonia; Rathish Chandran; Kalyana Chakravarthy; Uttpal D. Desai; Sumedha Limaye; Puneesh Puri; David R. Mulvihill; Mike Bichan; Martin Koolhaas; Vijayalakshmi Ramachandran; et al. (ISSCC, 2025)