Optimal Body Bias to Control Stability, Leakage and Speed in SRAM Cell. - Rohit Lorenzo; Saurabh Chaudhury (J. Circuits Syst. Comput., 2016)

Dynamic Threshold Sleep Transistor Technique for High Speed and Low Leakage in CMOS Circuits. - Rohit Lorenzo; Saurabh Chaudhury (Circuits Syst. Signal Process., 2017)

A Novel SRAM Cell Design with a Body-Bias Controller Circuit for Low Leakage, High Speed and Improved Stability. - Rohit Lorenzo; Saurabh Chaudhury (Wirel. Pers. Commun., 2017)

Low Power 10T SRAM Cell with Improved Stability Solving Soft Error Issue. - Rohit Lorenzo; Roy Paily (TENCON, 2019)

Single bit-line 11T SRAM cell for low power and improved stability. - Rohit Lorenzo; Roy Pailly (IET Comput. Digit. Tech., 2020)

Half-selection disturbance free 8T low leakage SRAM cell. - Rohit Lorenzo; Roy Paily (Int. J. Circuit Theory Appl., 2022)

A Soft Error Upset Recovery SRAM Cell for Aerospace and Military Applications. - Mukku Pavan Kumar; Rohit Lorenzo (TENCON, 2023)

Double Node Upset Immune RHBD-14T SRAM Cell for Space and Satellite Applications. - Mukku Pavan Kumar; Rohit Lorenzo (IEEE Access, 2023)

A review on radiation-hardened memory cells for space and terrestrial applications. - Mukku Pavan Kumar; Rohit Lorenzo (Int. J. Circuit Theory Appl., 2023)

Comprehensive Analysis of a Power-Efficient 1-Bit Hybrid Full Adder Cell. - Ayush Kanojia; Sachin Agrawal; Rohit Lorenzo (Wirel. Pers. Commun., 2023)

A Novel 18T Hybrid Master-Slave Flip-Flop With Low Power and Delay. - G. Rajesh Krishna; Rohit Lorenzo (IEEE Access, 2024)

A robust radiation resistant SRAM cell for space and military applications. - Mukku Pavan Kumar; Rohit Lorenzo (Integr., 2024)

Schmitt Trigger-Based Low Leakage and Half-Select Free Near-Threshold 10T SRAM Architecture. - Appikatla Phani Kumar; Rohit Lorenzo; Erfan Abbasian; Ashish Sachdeva (J. Circuits Syst. Comput., 2025)

Single-Ended Near Threshold 9T SRAM for Portable Low-Power Biomedical Applications. - Appikatla Phani Kumar; Rohit Lorenzo (J. Circuits Syst. Comput., 2025)