A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors. - Avinash K. Gautam; Jagdish C. Rao; Rohit Rathi; H. Udayakumar (VLSI Design, 1999)

A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips. - Ramin Farjad-Rad; William J. Dally; Hiok-Tiaq Ng; Ramesh Senthinathan; Ming-Ju Edward Lee; Rohit Rathi; John Poulton (IEEE J. Solid State Circuits, 2002)

A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. - Hiok-Tiaq Ng; Ming-Ju Edward Lee; Ramin Farjad-Rad; Ramesh Senthinathan; William J. Dally; Anhtuyet Nguyen; Rohit Rathi; Trey Greer; John Poulton; John H. Edmondson; James Tran (CICC, 2003)

A second-order semidigital clock recovery circuit based on injection locking. - Hiok-Tiaq Ng; Ramin Farjad-Rad; Ming-Ju Edward Lee; William J. Dally; Trey Greer; John Poulton; John H. Edmondson; Rohit Rathi; Ramesh Senthinathan (IEEE J. Solid State Circuits, 2003)

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. - Ramin Farjad-Rad; Anhtuyet Nguyen; James Tran; Trey Greer; John Poulton; William J. Dally; John H. Edmondson; Ramesh Senthinathan; Rohit Rathi; Ming-Ju Edward Lee; Hiok-Tiaq Ng (IEEE J. Solid State Circuits, 2004)