Abstract state machines as an intermediate representation for high-level synthesis. - Rohit Sinha 001; Hiren D. Patel (DATE, 2011)

Extending Force-Directed Scheduling with Explicit Parallel and Timed Constructs for High-Level Synthesis. - Rohit Sinha 001; Hiren D. Patel (FCCM, 2011)

Parallel simulation of mixed-abstraction SystemC models on GPUs and multicore CPUs. - Rohit Sinha 001; Aayush Prakash; Hiren D. Patel (ASP-DAC, 2012)

Verification with small and short worlds. - Rohit Sinha 001; Cynthia Sturton; Petros Maniatis; Sanjit A. Seshia; David A. Wagner 001 (FMCAD, 2012)

synASM: A High-Level Synthesis Framework With Support for Parallel and Timed Constructs. - Rohit Sinha 001; Hiren D. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Symbolic software model validation. - Cynthia Sturton; Rohit Sinha 001; Thurston H. Y. Dang; Sakshi Jain; Michael McCoyd; Wei Yang Tan; Petros Maniatis; Sanjit A. Seshia; David A. Wagner 001 (MEMOCODE, 2013)

Formal Modeling and Verification of CloudProxy. - Wei Yang Tan; Rohit Sinha 001; John L. Manferdelli; Sanjit A. Seshia (VSTTE, 2014)

Automatic Rootcausing for Program Equivalence Failures in Binaries. - Shuvendu K. Lahiri; Rohit Sinha 001; Chris Hawblitzel (CAV (1), 2015)

Moat: Verifying Confidentiality of Enclave Programs. - Rohit Sinha 001; Sriram K. Rajamani; Sanjit A. Seshia; Kapil Vaswani (CCS, 2015)

A design and verification methodology for secure isolated regions. - Rohit Sinha 001; Manuel Costa; Akash Lal; Nuno P. Lopes; Sriram K. Rajamani; Sanjit A. Seshia; Kapil Vaswani (PLDI, 2016)

A compiler and verifier for page access oblivious computation. - Rohit Sinha 001; Sriram K. Rajamani; Sanjit A. Seshia (ESEC/SIGSOFT FSE, 2017)

A Formal Foundation for Secure Remote Execution of Enclaves. - Pramod Subramanyan; Rohit Sinha 001; Ilia A. Lebedev; Srinivas Devadas; Sanjit A. Seshia (IACR Cryptol. ePrint Arch., 2017)

Secure Computing using Certified Software and Trusted Hardware. - Rohit Sinha 001 (2017)

VeritasDB: High Throughput Key-Value Store with Integrity. - Rohit Sinha 001; Mihai Christodorescu (IACR Cryptol. ePrint Arch., 2018)

LucidiTEE: Policy-based Fair Computing at Scale. - Rohit Sinha 001; Sivanarayana Gaddam; Ranjit Kumaresan (IACR Cryptol. ePrint Arch., 2019)

Verification of Quantitative Hyperproperties Using Trace Enumeration Relations. - Shubham Sahai; Pramod Subramanyan; Rohit Sinha 001 (CAV (1), 2020)

TEMP: Time-locked Encryption Made Practical. - Leemon Baird; Pratyay Mukherjee; Rohit Sinha 001 (IACR Cryptol. ePrint Arch., 2021)

Amortized Threshold Symmetric-key Encryption. - Mihai Christodorescu; Sivanarayana Gaddam; Pratyay Mukherjee; Rohit Sinha 001 (IACR Cryptol. ePrint Arch., 2021)

Reducing HSM Reliance in Payments through Proxy Re-Encryption. - Sivanarayana Gaddam; Atul Luykx; Rohit Sinha 001; Gaven J. Watson (IACR Cryptol. ePrint Arch., 2021)

i-TiRE: Incremental Timed-Release Encryption or How to use Timed-Release Encryption on Blockchains? - Leemon Baird; Pratyay Mukherjee; Rohit Sinha 001 (CCS, 2022)

Cryptography with Weights: MPC, Encryption and Signatures. - Sanjam Garg; Abhishek Jain 002; Pratyay Mukherjee; Rohit Sinha 001; Mingyuan Wang 001; Yinuo Zhang (IACR Cryptol. ePrint Arch., 2022)

LucidiTEE: Scalable Policy-Based Multiparty Computation with Fairness. - Sivanarayana Gaddam; Ranjit Kumaresan; Srinivasan Raghuraman; Rohit Sinha 001 (CANS, 2023)

Threshold Signatures in the Multiverse. - Leemon Baird; Sanjam Garg; Abhishek Jain 002; Pratyay Mukherjee; Rohit Sinha 001; Mingyuan Wang 001; Yinuo Zhang (IACR Cryptol. ePrint Arch., 2023)

How to Design Fair Protocols in the Multi-Blockchain Setting. - Sivanarayana Gaddam; Ranjit Kumaresan; Srinivasan Raghuraman; Rohit Sinha 001 (IACR Cryptol. ePrint Arch., 2023)

hinTS: Threshold Signatures with Silent Setup. - Sanjam Garg; Abhishek Jain 002; Pratyay Mukherjee; Rohit Sinha 001; Mingyuan Wang 001; Yinuo Zhang (IACR Cryptol. ePrint Arch., 2023)

HiSE: Hierarchical (Threshold) Symmetric-key Encryption. - Pousali Dey; Pratyay Mukherjee; Swagata Sasmal; Rohit Sinha 001 (IACR Cryptol. ePrint Arch., 2024)

Insta-Pok3r: Real-time Poker on Blockchain. - Sanjam Garg; Aniket Kate; Pratyay Mukherjee; Rohit Sinha 001; Sriram Sridhar 004 (IACR Cryptol. ePrint Arch., 2024)

SublonK: Sublinear Prover PlonK. - Arka Rai Choudhuri; Sanjam Garg; Aarushi Goel; Sruthi Sekar; Rohit Sinha 001 (Proc. Priv. Enhancing Technol., 2024)

Jigsaw: Doubly Private Smart Contracts. - Sanjam Garg; Aarushi Goel; Dimitris Kolonelos; Rohit Sinha 001 (IACR Cryptol. ePrint Arch., 2025)

Split Prover Zero-Knowledge SNARKs. - Sanjam Garg; Aarushi Goel; Dimitris Kolonelos; Sina Shiehian; Rohit Sinha 001 (IACR Cryptol. ePrint Arch., 2025)