Deductive Fault Simulation for Asynchronous Sequential Circuits. - Roland Dobai; Elena Gramatová (DSD, 2009)

Test pattern generation for the combinational representation of asynchronous circuits. - Roland Dobai; Elena Gramatová (DDECS, 2010)

Deductive Fault Simulation Technique for Asynchronous Circuits. - Roland Dobai; Elena Gramatová (Comput. Informatics, 2010)

A novel automatic test pattern generator for asynchronous sequential digital circuits. - Roland Dobai; Elena Gramatová (Microelectron. J., 2011)

Genetic method for compressed skewed-load delay test generation. - Roland Dobai; Marcel Baláz (DDECS, 2012)

Automated Generation of Built-In Self-Repair Architectures for Random Logic SoC Cores. - Roland Dobai; Marcel Baláz; Mária Fischerová (DSD, 2012)

Image filter evolution on the Xilinx Zynq Platform. - Roland Dobai; Lukás Sekanina (AHS, 2013)

Towards evolvable systems based on the Xilinx Zynq platform. - Roland Dobai; Lukás Sekanina (ICES, 2013)

Compressed Skewed-Load Delay Test Generation Based on Evolution and Deterministic Initialization of Populations. - Roland Dobai; Marcel Baláz (Comput. Informatics, 2013)

SAT-based generation of compressed skewed-load tests for transition delay faults. - Roland Dobai; Marcel Baláz (Microprocess. Microsystems, 2013)

Evolutionary on-line synthesis of hardware accelerators for software modules in reconfigurable embedded systems. - Roland Dobai (FPL, 2014)

Evolutionary digital circuit design with fast candidate solution establishment in field programmable gate arrays. - Roland Dobai; Kyrre Glette; Jim Tørresen; Lukás Sekanina (ICES, 2014)

Evolution of Non-Cryptographic Hash Function Pairs for FPGA-Based Network Applications. - Roland Dobai; Jan Korenek (SSCI, 2015)

Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware. - Roland Dobai; Lukás Sekanina (ACM Trans. Reconfigurable Technol. Syst., 2015)

Adaptive development of hash functions in FPGA-based network routers. - Roland Dobai; Jan Korenek; Lukás Sekanina (SSCI, 2016)

Evolutionary design of hash functions for IP address hashing using genetic programming. - Marek Kidon; Roland Dobai (CEC, 2017)

Designing bent boolean functions with parallelized linear genetic programming. - Jakub Husa; Roland Dobai (GECCO (Companion), 2017)

Evolutionary design of hash function pairs for network filters. - Roland Dobai; Jan Korenek; Lukás Sekanina (Appl. Soft Comput., 2017)

Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques. - Vojtech Mrazek; Lukás Sekanina; Roland Dobai; Marek Sýs; Petr Svenda (IEEE Trans. Very Large Scale Integr. Syst., 2019)