Single input current-sensing differential logic (SCSDL). - Roland Strandberg; Jiren Yuan (ISCAS, 2000)

Bandwidth considerations for a CALLUM transmitter architecture. - Roland Strandberg; Pietro Andreani; Lars Sundström (ISCAS (4), 2002)

A 9-band WCDMA/EDGE transceiver supporting HSPA evolution. - Magnus Nilsson; Sven Mattisson; Nikolaus Klemmer; Martin Anderson; Torkel Arnborg; Peter Caputa; Staffan Ek; Lin Fan; Henrik Fredriksson; Fabien Garrigues; Henrik Geis; Hans Hagberg; et al. (ISSCC, 2011)

A 4.75-34.75 MHz digitally tunable active-RC LPF for >60dB mean RX IRR in 65nm CMOS. - Martin Anderson; Roland Strandberg; Staffan Ek; Leif R. Wilhelmsson; Lars Sundström; Mattias Andersson 003; Imad ud Din; Jim Svensson; Thomas Olsson 001; Daniel Eckerbert (ESSCIRC, 2012)

A receiver for LTE Rel-11 and beyond supporting non-contiguous carrier aggregation. - Lars Sundström; Martin Anderson; Roland Strandberg; Staffan Ek; Jim Svensson; Fenghao Mu; Thomas Olsson 001; Imad ud Din; Leif R. Wilhelmsson; Daniel Eckerbert; Sven Mattisson (ISSCC, 2013)

Design of a Configurable Complex IF Receiver Supporting LTE Carrier Aggregation. - Leif R. Wilhelmsson; Jim Svensson; Martin Anderson; Staffan Ek; Roland Strandberg; Lars Sundström (VTC Spring, 2013)

Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS. - Lars Sundström; Staffan Ek; Jim Svensson; Martin Anderson; Roland Strandberg; Fenghao Mu; Imad ud Din; Thomas Olsson 001; Leif R. Wilhelmsson; Daniel Eckerbert (IEEE J. Solid State Circuits, 2013)

A 12b, 1 GSps TI pipelined-SAR converter with 65 dB SFDR through buffer linearization and gain mismatch correction in 28nm FD-SOI. - Mattias Palm; Daniele Mastantuono; Roland Strandberg; Lars Sundström; Sven Mattisson (ESSCIRC, 2017)

A 10-Bit Split-Capacitor SAR ADC with DAC Imbalance Estimation and Calibration. - Siyu Tan; Daniele Mastantuono; Roland Strandberg; Lars Sundström; Pietro Andreani; Mattias Palm (ISCAS, 2020)

A Design Method to Minimize the Impact of Bit Conversion Errors in SAR ADCs. - Siyu Tan; Mattias Palm; Daniele Mastantuono; Roland Strandberg; Lars Sundström; Sven Mattisson; Pietro Andreani (NorCAS, 2020)

A Bang-Bang Digital PLL Covering 11.1-14.3 GHz and 14.7-18.7 GHz with sub-40 fs RMS Jitter in 7 nm FinFET Technology. - Staffan Ek; Patrik Karlsson; Andreas Kämpe; Roland Strandberg; Aravind Tharayil Narayanan; Martin Anderson; Hind Dafallah; Mesrop Daghbashyan; Tayebeh Ghanavati Nejad; Robert Hägglund; Nikola Ivanisevic; Robert Nilsson; et al. (ESSCIRC, 2022)

A 12/16 GSps Time-Interleaved Pipelined-SAR ADC with Temperature Robust Performance at 0.75V Supply in 7nm FinFET Technology. - Mattias Palm; Daniele Mastantuono; Christer Jansson; Erik Backenius; Nikola Ivanisevic; Mikael Normark; Prakash Harikumar; My-Chien Yee; Andreas Leidenhed; Roland Strandberg; Sunny Sharma; Hanie Ghaedrahmati; et al. (ESSCIRC, 2023)