A 1.8-GHz instruction window buffer for an out-of-order microprocessor core. - Jens Leenstra; Jürgen Pille; Antje Müller; Wolfram M. Sauer; Rolf Sautter; Dieter F. Wendel (IEEE J. Solid State Circuits, 2001)

The vector fixed point unit of the synergistic processor element of the cell architecture processor. - Nicolas Mäding; Jens Leenstra; Jürgen Pille; Rolf Sautter; Stefan Büttner; Sebastian Ehrenreich; W. Haller (ESSCIRC, 2005)

A 32nm 0.5V-supply dual-read 6T SRAM. - Jente B. Kuang; Jeremy D. Schaub; Fadi H. Gebara; Dieter F. Wendel; Sudesh Saroop; Tuyet Nguyen; Thomas Fröhnel; Antje Müller; Christopher M. Durham; Rolf Sautter; Bryan Lloyd; Bryan J. Robbins; et al. (CICC, 2010)

A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor. - Jürgen Pille; Dieter F. Wendel; Otto Wagner; Rolf Sautter; Wolfgang Penth; Thomas Fröhnel; Stefan Büttner; Otto A. Torreiter; Martin Eckert; Jose Paredes; David Hrusecky; David Ray; et al. (ISSCC, 2010)

A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction. - Alexander Fritsch; Michael Kugel; Rolf Sautter; Dieter F. Wendel; Juergen Pille; Otto A. Torreiter; Shankar Kalyanasundaram; Daniel A. Dobson (ESSCIRC, 2015)

A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology. - Philipp Salz; A. Frisch; Wolfgang Penth; J. Noack; T. Kalla; Rolf Sautter; Michael Kugel; Otto A. Torreiter; G. Sapp; Mike Lee; Eric Fluhr; A. Rozenfeld; et al. (ESSCIRC, 2017)