Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks. - Romain Ritzenthaler; Tom Schram; Erik Bury; Jérôme Mitard; L.-Å. Ragnarsson; Guido Groeseneken; N. Horiguchi; Aaron Thean; Alessio Spessot; Christian Caillat; V. Srividya; Pierre Fazan (ESSDERC, 2012)

Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors. - Marc Aoulaiche; Eddy Simoen; Romain Ritzenthaler; Tom Schram; Hiroaki Arimura; Moonju Cho; Thomas Kauerauf; Guido Groeseneken; Naoto Horiguchi; Aaron Thean; Antonio Federico; Felice Crupi; et al. (ESSDERC, 2013)

STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process. - Doyoung Jang; Marie Garcia Bardon; Dmitry Yakimets; Kenichi Miyaguchi; An De Keersgieter; Thomas Chiarella; Romain Ritzenthaler; Morin Dehan; Abdelkarim Mercha (ESSDERC, 2013)

Impact of Off State Stress on advanced high-K metal gate NMOSFETs. - Alessio Spessot; Marc Aoulaiche; Moonju Cho; Jacopo Franco; Tom Schram; Romain Ritzenthaler; Ben Kaczer (ESSDERC, 2014)

Off-state stress degradation mechanism on advanced p-MOSFETs. - Moonju Cho; Alessio Spessot; Ben Kaczer; Marc Aoulaiche; Romain Ritzenthaler; Tom Schram; Pierre Fazan; Naoto Horiguchi; Dimitri Linten (ICICDT, 2015)

I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration. - Romain Ritzenthaler; Tom Schram; M. J. Cho; Anda Mocuta; Naoto Horiguchi; Aaron Voon-Yew Thean; Alessio Spessot; Christian Caillat; Marc Aoulaiche; Pierre Fazan; K. B. Noh; Y. Son (ICICDT, 2015)

Assessment of SiGe quantum well transistors for DRAM peripheral applications. - Romain Ritzenthaler; Tom Schram; Geert Eneman; Anda Mocuta; Naoto Horiguchi; Aaron Voon-Yew Thean; Alessio Spessot; Marc Aoulaiche; Pierre Fazan; K. B. Noh; Y. Son (ICICDT, 2015)

Reliability impact of advanced doping techniques for DRAM peripheral MOSFETs. - Alessio Spessot; Romain Ritzenthaler; Tom Schram; Marc Aoulaiche; Moonju Cho; Maria Toledano-Luque; Naoto Horiguchi; Pierre Fazan (ICICDT, 2015)

NBTI in Si0.55Ge0.45 cladding p-FinFETs: Porting the superior reliability from planar to 3D architectures. - Jacopo Franco; Ben Kaczer; Philippe J. Roussel; Erik Bury; Hans Mertens; Romain Ritzenthaler; Tibor Grasser; Naoto Horiguchi; Aaron Thean; Guido Groeseneken (IRPS, 2015)

Towards high performance sub-10nm finW bulk FinFET technology. - Thomas Chiarella; Stefan Kubicek; E. Rosseel; Romain Ritzenthaler; Andriy Hikavyy; P. Eyben; An De Keersgieter; L.-Å. Ragnarsson; M.-S. Kim; S.-A. Chew; Tom Schram; S. Demuynck; et al. (ESSDERC, 2016)

PPAC scaling enablement for 5nm mobile SoC technology. - Mustafa Badaroglu; Jeff Xu; John Zhu; Da Yang 007; Jerry Bao; Seung Chul Song; Peijie Feng; Romain Ritzenthaler; Hans Mertens; Geert Eneman; Naoto Horiguchi; Jeffrey Smith 003; et al. (ESSDERC, 2017)

Isolation of nanowires made on bulk wafers by ground plane doping. - Romain Ritzenthaler; Hans Mertens; An De Keersgieter; Jérôme Mitard; Dan Mocuta; N. Horiguchi (ESSDERC, 2017)

Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors. - Eddy Simoen; Alberto Vinicius Oliveira; Anabela Veloso; Adrian Vaisman Chasin; Romain Ritzenthaler; Hans Mertens; Naoto Horiguchi; Cor Claeys (ASICON, 2019)

Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices. - Barry J. O'Sullivan; Romain Ritzenthaler; Gerhard Rzepa; Z. Wu; E. Dentoni Litta; O. Richard; T. Conard; V. Machkaoutsan; Pierre Fazan; C. Kim; Jacopo Franco; Ben Kaczer; et al. (IRPS, 2019)

Relevance of fin dimensions and high-pressure anneals on hot-carrier degradation. - Adrian Vaisman Chasin; Jacopo Franco; Erik Bury; Romain Ritzenthaler; Eugenio Dentoni Litta; Alessio Spessot; Naoto Horiguchi; Dimitri Linten; Ben Kaczer (IRPS, 2020)

Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations. - Alessio Spessot; Shairfe Muhammad Salahuddin; Ricardo Escobar; Romain Ritzenthaler; Yang Xiang; Rahul Budhwani; Eugenio Dentoni Litta; Elena Capogreco; Joao P. Bastos; Yangyin Chen; Naoto Horiguchi (IMW, 2022)

Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery. - J. P. Bastos; Barry J. O'Sullivan; Jacopo Franco; Stanislav Tyaginov; Brecht Truijen; Adrian Vaisman Chasin; Robin Degraeve; Ben Kaczer; Romain Ritzenthaler; Elena Capogreco; E. Dentoni Litta; Alessio Spessot; et al. (IRPS, 2022)

Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets. - Erik Bury; Adrian Vaisman Chasin; Ben Kaczer; Michiel Vandemaele; Stanislav Tyaginov; Jacopo Franco; Romain Ritzenthaler; Hans Mertens; Pieter Weckx; N. Horiguchi; Dimitri Linten (IRPS, 2022)

High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories. - Romain Ritzenthaler; Elena Capogreco; E. Dupuy; Hiroaki Arimura; J. P. Bastos; P. Favia; F. Sebaai; D. Radisic; V. T. H. Nguyen; G. Mannaert; B. T. Chan; V. Machkaoutsan; et al. (VLSI Technology and Circuits, 2022)

Reliability challenges in Forksheet Devices: (Invited Paper). - Erik Bury; Michiel Vandemaele; Jacopo Franco; Adrian Chasin; Stanislav Tyaginov; A. Vandooren; Romain Ritzenthaler; Hans Mertens; Javier Diaz-Fortuny; N. Horiguchi; Dimitri Linten; Ben Kaczer (IRPS, 2023)

Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions. - Jacopo Franco; Hiroaki Arimura; J.-F. de Marneffe; S. Brus; Romain Ritzenthaler; E. Dentoni Litta; Kris Croes; Ben Kaczer; N. Horiguchi (VLSI Technology and Circuits, 2023)

DRAM-Peri FinFET - A Thermally-Stable High-Performance Advanced CMOS RMG Platform with Mo-Based pWFM for sub-10nm DRAM. - J. Ganguly; Hiroaki Arimura; Romain Ritzenthaler; H. Bana; J. W. Maes; J. G. Lai; S. Brus; W. Maqsood; R. Sarkar; B. Kannan; Elena Capogreco; V. Machkaoutsan; et al. (VLSI Technology and Circuits, 2024)