An approach to minimal-time scheduling of micro-operations. - Alfonso Sotelo; Julio Septién; Román Hermida; Milagros Fernández (Microprocessing and Microprogramming, 1990)

A hardware allocator guided by cost functions. - J. Septiéna; Daniel Mozos; Román Hermida; Francisco Tirado (Microprocessing and Microprogramming, 1991)

Heuristics for branch-and-bound global allocation. - Julio Septién; Daniel Mozos; Francisco Tirado; Román Hermida; Milagros Fernández (EURO-DAC, 1992)

Design control in a high level synthesis system. - Daniel Mozos; Julio Septién; Francisco Tirado; Román Hermida (Microprocess. Microprogramming, 1992)

An approach to module binding by fuzzy partitioning. - Román Hermida; Milagros Fernández; Francisco Tirado; Victor Manuel Sanchez; Pablo Ruperez (EURO-DAC, 1993)

Global hardware synthesis guided by realistic probability computation. - R. Moreno; Román Hermida; Daniel Mozos; Katzalin Olcoz (Microprocess. Microprogramming, 1993)

Clock cycle estimation based on dead time and control unit area minimization. - Hortensia Mecha; Milagros Fernández; Román Hermida; Daniel Mozos; Katzalin Olcoz (Microprocess. Microprogramming, 1994)

Algebraic Support for Transformational Hardware Allocation. - José M. Mendías; Román Hermida; Milagros Fernández (ED&TC, 1996)

Register estimation in unscheduled dataflow graphs. - R. Moreno; Román Hermida; Milagros Fernández (ACM Trans. Design Autom. Electr. Syst., 1996)

Formal Techniques for Hardware Allocation. - José M. Mendías; Román Hermida; Milagros Fernández (VLSI Design, 1997)

A unified approach for scheduling and allocation. - R. Moreno; Román Hermida; Milagros Fernández; Hortensia Mecha (Integr., 1997)

Correct High-Level Synthesis: a Formal Perspective. - José M. Mendías; Román Hermida (DATE, 1998)

RSR: A New Rectilinear Steiner Minimum Tree Approximation for FPGA Placement and Global Routing. - Juan de Vicente; Juan Lanchares; Román Hermida (EUROMICRO, 1998)

Kernel Scheduling in Reconfigurable Computing. - Rafael Maestre; Fadi J. Kurdahi; Nader Bagherzadeh; Hartej Singh; Román Hermida; Milagros Fernández (DATE, 1999)

The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach. - Juan Antonio Maestro; Daniel Mozos; Román Hermida (DATE, 1999)

A Unified Algorithm for Mutual Exclusiveness Identification. - Olga Peñalba; José M. Mendías; Román Hermida (EUROMICRO, 1999)

Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies. - Juan de Vicente; Juan Lanchares; Román Hermida (FPL, 1999)

A Framework for Scheduling and Context Allocation in Reconfigurable Computing. - Rafael Maestre; Milagros Fernández; Román Hermida; Nader Bagherzadeh (ISSS, 1999)

Partitioning and Placement for Multi-FPGA Systems Using Genetic Algorithms. - José Ignacio Hidalgo; Juan Lanchares; Román Hermida (EUROMICRO, 2000)

Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. - Rafael Maestre; Milagros Fernández; Román Hermida; Fadi J. Kurdahi; Nader Bagherzadeh; Hartej Singh (FCCM, 2000)

Adaptive FPGA Placement by Natural Optimization. - Juan de Vicente; Juan Lanchares; Román Hermida (IEEE International Workshop on Rapid System Prototyping, 2000)

A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits. - Oscar Garnica; Juan Lanchares; Román Hermida (DATE, 2001)

A data scheduler for multi-context reconfigurable architectures. - Marcos Sánchez-Élez; Milagros Fernández; Román Hermida; Rafael Maestre; Fadi J. Kurdahi; Nader Bagherzadeh (ISSS, 2001)

Kernel scheduling techniques for efficient solution space exploration in reconfigurable computing. - Rafael Maestre; Fadi J. Kurdahi; Milagros Fernández; Román Hermida; Nader Bagherzadeh; Hartej Singh (J. Syst. Archit., 2001)

A formal approach to context scheduling for multicontext reconfigurable architectures. - Rafael Maestre; F. Kurdahl; Milagros Fernández; Román Hermida; Nader Bagherzadeh; Hartej Singh (IEEE Trans. Very Large Scale Integr. Syst., 2001)

A framework for reconfigurable computing: task scheduling and context management. - Rafael Maestre; Fadi J. Kurdahi; Milagros Fernández; Román Hermida; Nader Bagherzadeh; Hartej Singh (IEEE Trans. Very Large Scale Integr. Syst., 2001)

High-level synthesis of multiple-precision circuitsindependent of data-objects length. - María C. Molina; José M. Mendías; Román Hermida (DAC, 2002)

Multiple-Precision Circuits Allocation Independent of Data-Objects Length. - María C. Molina; José M. Mendías; Román Hermida (DATE, 2002)

Maximizing Conditonal Reuse by Pre-Synthesis Transformations. - Olga Peñalba; José M. Mendías; Román Hermida (DATE, 2002)

A Complete Data Scheduler for Multi-Context Reconfigurable Architectures. - Marcos Sánchez-Élez; Milagros Fernández; Rafael Maestre; Román Hermida; Nader Bagherzadeh; Fadi J. Kurdahi (DATE, 2002)

FPGA Placement by Thermodynamic Combinatorial Optimization. - Juan de Vicente; Juan Lanchares; Román Hermida (DATE, 2002)

A Hybrid Evolutionary Algorithm for Multi-FPGA Systems Design. - José Ignacio Hidalgo; Juan Lanchares; Aitor Ibarra; Román Hermida (DSD, 2002)

Optimization of Equational Specifications Using Genetic Techniques. - Aitor Ibarra; José M. Mendías; Juan Lanchares; José Ignacio Hidalgo; Román Hermida (DSD, 2002)

Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis. - José M. Mendías; Román Hermida; María C. Molina; Olga Peñalba (DSD, 2002)

Bit-Level Allocation of Multiple-Precision Specifications. - María C. Molina; José M. Mendías; Román Hermida (DSD, 2002)

Source Code Transformation to Improve Conditional Hardware Reuse. - Olga Peñalba; José M. Mendías; Román Hermida (DSD, 2002)

Transformation of Equational Specification by Means of Genetic Programming. - Aitor Ibarra; Juan Lanchares; Jose Manuel Mendias; José Ignacio Hidalgo; Román Hermida (EuroGP, 2002)

Bit-level scheduling of heterogeneous behavioural specifications. - María C. Molina; José M. Mendías; Román Hermida (ICCAD, 2002)

A New Methodology to Design Low-Power Asynchronous Circuits. - Oscar Garnica; Juan Lanchares; Román Hermida (PATMOS, 2002)

Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. - Oscar Garnica; Juan Lanchares; Román Hermida (Fundam. Informaticae, 2002)

A study about the efficiency of formal high-level synthesis applied to verification. - José M. Mendías; Román Hermida; Olga Peñalba (Integr., 2002)

A global approach to improve conditional hardware reuse in high-level synthesis. - Olga Peñalba; José M. Mendías; Román Hermida (J. Syst. Archit., 2002)

High-Level Allocation to Minimize Internal Hardware Wastage. - María C. Molina; José M. Mendías; Román Hermida (DATE, 2003)

Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures. - Marcos Sánchez-Élez; Milagros Fernández; Manuel L. Anido; Haitao Du; Nader Bagherzadeh; Román Hermida (DATE, 2003)

Multi-FPGA Systems Synthesis by Means of Evolutionary Computation. - José Ignacio Hidalgo; Francisco Fernández 001; Juan Lanchares; Juan Manuel Sánchez-Pérez; Román Hermida; Marco Tomassini; Ranieri Baraglia; Raffaele Perego 001; Oscar Garnica (GECCO, 2003)

Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization. - Sonia López; Oscar Garnica; José Ignacio Hidalgo; Juan Lanchares; Román Hermida (PATMOS, 2003)

Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis. - María C. Molina; Rafael Ruiz-Sautua; José M. Mendías; Román Hermida (PATMOS, 2003)

Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources. - María C. Molina; José M. Mendías; Román Hermida (J. Syst. Archit., 2003)

Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures. - Fredy Rivera; Marcos Sánchez-Élez; Milagros Fernández; Román Hermida; Nader Bagherzadeh (CODES+ISSS, 2004)

Behavioural Bitwise Scheduling Based on Computational Effort Balancing. - María C. Molina; Rafael Ruiz-Sautua; José M. Mendías; Román Hermida (DATE, 2004)

Behavioural Scheduling to Balance the Bit-Level Computational Effort. - María C. Molina; Rafael Ruiz-Sautua; José M. Mendías; Román Hermida (ISVLSI, 2004)

Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays. - José Manuel Colmenar; Oscar Garnica; Sonia López; José Ignacio Hidalgo; Juan Lanchares; Román Hermida (PDP, 2004)

Annealing placement by thermodynamic combinatorial optimization. - Juan de Vicente; Juan Lanchares; Román Hermida (ACM Trans. Design Autom. Electr. Syst., 2004)

Arrival time aware scheduling to minimize clock cycle length. - Rafael Ruiz-Sautua; María C. Molina; José M. Mendías; Román Hermida (ASP-DAC, 2005)

A Complete Network-On-Chip Emulation Framework. - Nicolas Genko; David Atienza; Giovanni De Micheli; Jose Manuel Mendias; Román Hermida; Francky Catthoor (DATE, 2005)

Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis. - Rafael Ruiz-Sautua; María C. Molina; José M. Mendías; Román Hermida (DATE, 2005)

Performance-driven read-after-write dependencies softening in high-level synthesis. - Rafael Ruiz-Sautua; María C. Molina; Jose Manuel Mendias; Román Hermida (ICCAD, 2005)

Low Power Data Prefetch for 3D Image Applications on Coarse-Grain Reconfigurable Architectures. - Fredy Rivera; Marcos Sánchez-Élez; Milagros Fernández; Román Hermida; Nader Bagherzadeh (IPDPS, 2005)

A novel approach for network on chip emulation. - Nicolas Genko; David Atienza; Giovanni De Micheli; Luca Benini; Jose Manuel Mendias; Román Hermida; Francky Catthoor (ISCAS (3), 2005)

Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs. - J. B. Pérez-Ramas; David Atienza; Miguel Peón-Quirós; Ivan Magan; Jose Manuel Mendias; Román Hermida (PARCO, 2005)

Pre-synthesis optimization of multiplications to improve circuit performance. - Rafael Ruiz-Sautua; María C. Molina; José M. Mendías; Román Hermida (DATE, 2006)

Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures. - Fredy Rivera; Marcos Sánchez-Élez; Milagros Fernández; Román Hermida; Nader Bagherzadeh (FPL, 2006)

Bitwise scheduling to balance the computational cost of behavioral specifications. - María C. Molina; Rafael Ruiz-Sautua; Jose Manuel Mendias; Román Hermida (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials. - José Luis Imaña; Román Hermida; Francisco Tirado (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Area optimization of multi-cycle operators in high-level synthesis. - María C. Molina; Rafael Ruiz-Sautua; Jose Manuel Mendias; Román Hermida (DATE, 2007)

HW-SW emulation framework for temperature-aware design in MPSoCs. - David Atienza; Pablo García Del Valle; Giacomo Paci; Francesco Poletti; Luca Benini; Giovanni De Micheli; Jose Manuel Mendias; Román Hermida (ACM Trans. Design Autom. Electr. Syst., 2007)

Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis. - Alberto A. Del Barrio; María C. Molina; Jose Manuel Mendias; Esther Andres Perez; Román Hermida (DSD, 2008)

Applying speculation techniques to implement functional units. - Alberto A. Del Barrio; María C. Molina; Jose Manuel Mendias; Esther Andres Perez; Román Hermida; Francisco Tirado (ICCD, 2008)

Scheduling methodology for conditional execution of kernels onto multicontext reconfigurable architectures. - Fredy Rivera; Marcos Sánchez-Élez; Román Hermida; Nader Bagherzadeh (IET Comput. Digit. Tech., 2008)

A framework for low energy data management in reconfigurable multi-context architectures. - Marcos Sánchez-Élez; Nader Bagherzadeh; Román Hermida (J. Syst. Archit., 2009)

Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications. - María C. Molina; Rafael Ruiz-Sautua; Pedro Garcia-Repetto; Román Hermida (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Using Speculative Functional Units in high level synthesis. - Alberto A. Del Barrio; María C. Molina; Jose Manuel Mendias; Román Hermida; Seda Ogrenci Memik (DATE, 2010)

Power optimization in heterogenous datapaths. - Alberto A. Del Barrio; Seda Ogrenci Memik; María C. Molina; José M. Mendías; Román Hermida (DATE, 2011)

A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis. - Alberto A. Del Barrio; Seda Ogrenci Memik; María C. Molina; Jose Manuel Mendias; Román Hermida (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Multispeculative Addition Applied to Datapath Synthesis. - Alberto A. Del Barrio; Román Hermida; Seda Ogrenci Memik; José M. Mendías; María C. Molina (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Multispeculative additive trees in high-level synthesis. - Alberto A. Del Barrio; Román Hermida; Seda Ogrenci Memik; Jose Manuel Mendias; María C. Molina (DATE, 2013)

Exploring the energy efficiency of Multispeculative Adders. - Alberto A. Del Barrio; Román Hermida; Seda Ogrenci Memik (ICCD, 2013)

A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths. - Alberto A. Del Barrio; Seda Ogrenci Memik; María C. Molina; José M. Mendías; Román Hermida (Integr., 2013)

Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials. - José Luis Imaña; Román Hermida; Francisco Tirado (Integr., 2013)

Generic Markov model of the contention access period of IEEE 802.15.4 MAC layer. - Joaquín Recas; Nadia Khaled; Alberto A. Del Barrio; Román Hermida (Digit. Signal Process., 2014)

Improving circuit performance with multispeculative additive trees in high-level synthesis. - Alberto A. Del Barrio; Román Hermida; Seda Ogrenci Memik; Jose Manuel Mendias; María C. Molina (Microelectron. J., 2014)

Ultra-low-power adder stage design for exascale floating point units. - Alberto A. Del Barrio; Nader Bagherzadeh; Román Hermida (ACM Trans. Embed. Comput. Syst., 2014)

Runtime data center temperature prediction using Grammatical Evolution techniques. - Marina Zapater; José L. Risco-Martín; Patricia Arroba; José L. Ayala; José Manuel Moya; Román Hermida (Appl. Soft Comput., 2016)

A Partial Carry-Save On-the-Fly Correction Multispeculative Multiplier. - Alberto A. Del Barrio; Román Hermida; Seda Ogrenci Memik (IEEE Trans. Computers, 2016)

A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis. - Alberto A. Del Barrio; Jason Cong; Román Hermida (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

A slack-based approach to efficiently deploy radix 8 booth multipliers. - Alberto A. Del Barrio; Román Hermida (DATE, 2017)

Reconsidering the performance of DEVS modeling and simulation environments using the DEVStone benchmark. - José L. Risco-Martín; Saurabh Mittal; Juan Carlos Fabero Jiménez; Marina Zapater; Román Hermida (Simul., 2017)

Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks. - Min Soo Kim 003; Alberto A. Del Barrio; Román Hermida; Nader Bagherzadeh (ASP-DAC, 2018)

Complexity reduction in the HEVC/H265 standard based on smooth region classification. - David Guillermo Fernández; Alberto A. Del Barrio; Guillermo Botella Juan; Carlos García 001; Manuel Prieto 001; Román Hermida (Digit. Signal Process., 2018)

A Modular Low-Complexity ECG Delineation Algorithm for Real-Time Embedded Systems. - Jose Manuel Bote; Joaquín Recas; Francisco J. Rincón; David Atienza; Román Hermida (IEEE J. Biomed. Health Informatics, 2018)

Modular framework to model critical events in stroke patients. - Kevin Henares; José L. Risco-Martín; Román Hermida; Gemma Reig Roselló; Román Cárdenas (SummerSim, 2019)

Efficient Mitchell's Approximate Log Multipliers for Convolutional Neural Networks. - Min Soo Kim 003; Alberto A. Del Barrio; Leonardo Tavares Oliveira; Román Hermida; Nader Bagherzadeh (IEEE Trans. Computers, 2019)

A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapaths. - Alberto A. Del Barrio; Román Hermida; Seda Ogrenci Memik (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Evaluation of blood pressure estimation models based on pulse arrival time. - Jose Manuel Bote; Joaquín Recas; Román Hermida (Comput. Electr. Eng., 2020)

Efficient micro data centres deployment for mobile healthcare monitoring systems in IoT urban scenarios. - Kevin Henares; José L. Risco-Martín; José L. Ayala; Román Hermida (J. Simulation, 2022)