Microbenchmarks for Detailed Validation and Tuning of Hardware Simulators. - Rommel Sánchez Verdejo; Petar Radojkovic (HPCS, 2017)

Enabling a reliable STT-MRAM main memory simulation. - Kazi Asifuzzaman; Rommel Sánchez Verdejo; Petar Radojkovic (MEMSYS, 2017)

Main memory latency simulation: the missing link. - Rommel Sánchez Verdejo; Kazi Asifuzzaman; Milan Radulovic; Petar Radojkovic; Eduard Ayguadé; Bruce L. Jacob (MEMSYS, 2018)

Rethinking cycle accurate DRAM simulation. - Shang Li 001; Rommel Sánchez Verdejo; Petar Radojkovic; Bruce L. Jacob (MEMSYS, 2019)

PROFET: Modeling System Performance and Energy Without Simulating the CPU. - Milan Radulovic; Rommel Sánchez Verdejo; Paul M. Carpenter; Petar Radojkovic; Bruce L. Jacob; Eduard Ayguadé (Proc. ACM Meas. Anal. Comput. Syst., 2019)

Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level Simulation. - Kazi Asifuzzaman; Rommel Sánchez Verdejo; Petar Radojkovic (ACM Trans. Embed. Comput. Syst., 2022)

HPC memory systems: Implications of system simulation and checkpointing. - Rommel Sánchez Verdejo (2022)