Fairness and Throughput in Switch on Event Multithreading. - Ron Gabor; Shlomo Weiss; Avi Mendelson (MICRO, 2006)

Fairness enforcement in switch on event multithreading. - Ron Gabor; Shlomo Weiss; Avi Mendelson (ACM Trans. Archit. Code Optim., 2007)

Service level agreement for multithreaded processors. - Ron Gabor; Avi Mendelson; Shlomo Weiss (ACM Trans. Archit. Code Optim., 2009)

Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core. - Ron Gabor; Yiannakis Sazeides; Arkady Bramnik; Alexandros Andreou; Chrysostomos Nicopoulos; Karyofyllis Patsidis; Dimitris Konstantinou; Giorgos Dimitrakopoulos (DATE, 2019)

2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD). - Yiannakis Sazeides; Arkady Bramnik; Ron Gabor; Chrysostomos Nicopoulos; Ramon Canal; Dimitris Konstantinou; Giorgos Dimitrakopoulos (DFT, 2020)

Speculative interference attacks: breaking invisible speculation schemes. - Mohammad Behnia; Prateek Sahu; Riccardo Paccagnella; Jiyong Yu; Zirui Neil Zhao; Xiang Zou; Thomas Unterluggauer; Josep Torrellas; Carlos V. Rozas; Adam Morrison 001; Frank McKeen; Fangfei Liu; et al. (ASPLOS, 2021)

IDLD: Instantaneous Detection of Leakage and Duplication of Identifiers used for Register Renaming. - Yiannakis Sazeides; Alex Gerber; Ron Gabor; Arkady Bramnik; George Papadimitriou 001; Dimitris Gizopoulos; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos; Karyofyllis Patsidis (MICRO, 2022)

A Real-Time Error Detection (RTD) Architecture and Its Use for Reliability and Post-Silicon Validation for F/F Based Memory Arrays. - Yiannakis Sazeides; Arkady Bramnik; Ron Gabor; Ramon Canal (IEEE Trans. Emerg. Top. Comput., 2022)