High-Frequency, At-Speed Scan Testing. - Xijiang Lin; Ron Press; Janusz Rajski; Paul Reuter; Thomas Rinderknecht; Bruce Swanson; Nagesh Tamarapalli (IEEE Des. Test Comput., 2003)

Achieving High Test Quality with Reduced Pin Count Testing. - Jay Jahangiri; Nilanjan Mukherjee 001; Wu-Tung Cheng; Subramanian Mahadevan; Ron Press (Asian Test Symposium, 2005)

Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. - Matthias Beck; Olivier Barondeau; Martin Kaibel; Frank Poehl; Xijiang Lin; Ron Press (DATE, 2005)

Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study. - Matthias Beck; Olivier Barondeau; Frank Poehl; Xijiang Lin; Ron Press (VTS, 2005)

Mentor Graphics DFT to Navigate Nanometer Test Challenges. - Greg Aldrich; Ron Press; Takeo Kobayashi; Tatsuo Sakajiri (ATS, 2006)

The Demand and Practical Approach for 100x Test Compression. - Ron Press; Jay Jahangiri (VLSI-SoC, 2006)

Scan Compression Implementation in Industrial Design - Case Study. - Dragon Hsu; Ron Press (Asian Test Symposium, 2009)

The ABCs of ITC. - Ron Press; Erik H. Volkerink (IEEE Des. Test Comput., 2010)

ITC and the Future of Test - We've Won. - Ron Press; Li-C. Wang (IEEE Des. Test, 2016)

Automotive IC On-line Test Techniques and the Application of Deterministic ATPG-Based Runtime Test. - Yoichi Maeda; Jun Matsushima; Ron Press (ATS, 2017)

Short Paper: Bus-based Packetized Scan Architecture Trade-offs for Heterogeneous Multi-Core SoCs. - Hiroyuki Iwata; Mahmoud AbdAlwahab; Ron Press; Ohki Sugiura (ITC, 2024)