A multithreaded PowerPC processor for commercial servers. - John M. Borkenhagen; Richard J. Eickemeyer; Ronald N. Kalla; Steven R. Kunkel (IBM J. Res. Dev., 2000)

Design and implementation of the POWER5 microprocessor. - Joachim G. Clabes; Joshua Friedrich; Mark Sweet; Jack DiLullo; Sam G. Chu; Donald W. Plass; James Dawson; Paul Muench; Larry Powell; Michael S. Floyd; Balaram Sinharoy; Mike Lee; et al. (DAC, 2004)

IBM Power5 Chip: A Dual-Core Multithreaded Processor. - Ronald N. Kalla; Balaram Sinharoy; Joel M. Tendler (IEEE Micro, 2004)

POWER5 system microarchitecture. - Balaram Sinharoy; Ronald N. Kalla; Joel M. Tendler; Richard J. Eickemeyer; Jody B. Joyner (IBM J. Res. Dev., 2005)

Soft-error resilience of the IBM POWER6 processor. - Pia N. Sanda; Jeffrey W. Kellington; Prabhakar Kudva; Ronald N. Kalla; Ryan B. McBeth; Jerry Ackaret; Ryan Lockwood; John Schumann; Christopher R. Jones (IBM J. Res. Dev., 2008)

POWER7: IBM's next generation server processor. - Ronald N. Kalla; Balaram Sinharoy (Hot Chips Symposium, 2009)

The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor. - Dieter F. Wendel; Ronald N. Kalla; Robert Cargnoni; Joachim G. Clabes; Joshua Friedrich; Roland Frech; James A. Kahle; Balaram Sinharoy; William J. Starke; Scott A. Taylor; Steve Weitzel; Sam G. Chu; et al. (ISSCC, 2010)

Power7: IBM's Next-Generation Server Processor. - Ronald N. Kalla; Balaram Sinharoy; William J. Starke; Michael S. Floyd (IEEE Micro, 2010)

POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. - Dieter F. Wendel; Ronald N. Kalla; James D. Warnock; Robert Cargnoni; Sam G. Chu; Joachim G. Clabes; Daniel Dreps; David Hrusecky; Joshua Friedrich; Md. Saiful Islam 004; James A. Kahle; Jens Leenstra; et al. (IEEE J. Solid State Circuits, 2011)

IBM POWER7+ processor on-chip accelerators for cryptography and active memory expansion. - Bart Blaner; Bülent Abali; Brian M. Bass; Suresh Chari; Ronald N. Kalla; Steven R. Kunkel; Kenneth Lauricella; Ross Leavens; John J. Reilly; Peter A. Sandon (IBM J. Res. Dev., 2013)

Debugging post-silicon fails in the IBM POWER8 bring-up lab. - Manoj Dusanapudi; S. Fields; Michael S. Floyd; Guy L. Guthrie; Ronald N. Kalla; Shakti Kapoor; Larry S. Leitner; Charles F. Marino; Joseph McGill; Amir Nahir; Kevin Reick; H. Shen; et al. (IBM J. Res. Dev., 2015)

IBM Power9 Processor Architecture. - Satish Kumar Sadasivam; Brian W. Thompto; Ronald N. Kalla; William J. Starke (IEEE Micro, 2017)

IBM POWER9 processor and system features for computing in the cognitive era. - L. Baba Arimilli; Bart Blaner; Ben C. Drerup; Charles F. Marino; Derek Williams; Eric N. Lais; Francesco A. Campisano; Guy L. Guthrie; Michael S. Floyd; Ross Leavens; Scot M. Willenborg; Ronald N. Kalla; et al. (IBM J. Res. Dev., 2018)