A Classification Approach for Automated Reasoning Systems-A Case Study in Graph Theory. - Rong Lin (1989)

Fast Parallel Algorithms for Cographs. - Rong Lin; Stephan Olariu (FSTTCS, 1990)

A fast NC algorithm to recognize P4-reducible graphs. - Rong Lin; Stephan Olariu (Jerusalem Conference on Information Technology, 1990)

On the parallel recognition of some tree-representable graphs. - Rong Lin; Stephan Olariu (SPDP, 1990)

A Fast Parallel, Algorithm to Recognize, Partitionable Graphs. - Rong Lin; Stephan Olariu (Inf. Process. Lett., 1990)

Optimal parallel coloring algorithms for a family of tree-representable graphs. - Rong Lin; Stephan Olariu (ACM Conference on Computer Science, 1991)

A Simple Optimal Parallel Algorithm to Solve the Lowest Common Ancestor Problem. - Rong Lin; Stephan Olariu (ICCI, 1991)

A Fast Parallel Algorithm to Compute Path Functions for Cographs. - Rong Lin; Stephan Olariu (ICPP (3), 1991)

Fast Algorithms for Lowest Common Ancestors on a Processor Array with Reconfigurable Buses. - Rong Lin (Inf. Process. Lett., 1991)

An NC Recognition Algorithm for Cographs. - Rong Lin; Stephan Olariu (J. Parallel Distributed Comput., 1991)

Computing the Inner Product on Reconfigurable Buses with Shift Switching. - Rong Lin; Stephan Olariu (CONPAR, 1992)

Reconfigurable Buses with Shift Switching - VLSI RADIX Sort. - Rong Lin (ICPP (3), 1992)

A fast cost-optimal parallel algorithm for the lowest common ancestor problem. - Rong Lin; Stephan Olariu (Parallel Comput., 1992)

A practical constant time sorting network. - Rong Lin; Stephan Olariu (ASAP, 1993)

Square Meshes Are Not Optimal For Convex Hull Computation. - Dharmavani Bhagavathi; Himabindu Gurla; Stephan Olariu; Rong Lin; James L. Schwing; Jingyuan Zhang (ICPP (3), 1993)

Simulating Enhanced Meshes, with Applications. - Rong Lin; Stephan Olariu; James L. Schwing; Jingyuan Zhang (Parallel Process. Lett., 1993)

An efficient VLSI architecture for digital geometry. - Rong Lin; Stephan Olariu; James L. Schwing (ASAP, 1994)

Convolution Computation on Shift Switching Buses. - Rong Lin (HICSS (2), 1994)

Time-Optimal Multiple Rank Computations on Meshes with Multiple Broadcasting. - Dharmavani Bhagavathi; Venkatavasu Bokka; Himabindu Gurla; Rong Lin; Stephan Olariu; James L. Schwing; W. Shen; Larry Wilson (ICPP (3), 1994)

Application-specific array processors for binary prefix sum computation. - Rong Lin; Stephan Olariu (SPDP, 1994)

An Optimal Parallel Matching Algorithm for Cographs. - Rong Lin; Stephan Olariu (J. Parallel Distributed Comput., 1994)

An Efficient Erew Algorithm for Minimum Path Cover and Hamiltonicity on Cographs. - Rong Lin; Stephan Olariu; James L. Schwing; Jingyuan Zhang (Parallel Algorithms Appl., 1994)

Computing on Reconfigurable Buses - A New Computational Paradigm. - Rong Lin; Stephan Olariu; James L. Schwing; Jingyuan Zhang (Parallel Process. Lett., 1994)

A simple array processor for binary prefix sums. - Rong Lin; Stephan Olariu (ASAP, 1995)

A Cost-optimal Erew Breadth-first Algorithm for Ordered Trees, with Applications. - Rong Lin; Stephan Olariu (Parallel Algorithms Appl., 1995)

Reconfigurable Buses with Shift Switching: Concepts and Applications. - Rong Lin; Stephan Olariu (IEEE Trans. Parallel Distributed Syst., 1995)

Fast multiplier schemes using large parallel counters and shift switches. - Rong Lin (HiPC, 1997)

Reconfigurable buses with shift switches for fast final additions of parallel multipliers. - Rong Lin (PDPTA, 1997)

A Scalable VLSI Architecture for Binary Prefix Sums. - Rong Lin; Koji Nakano; Stephan Olariu; Maria Cristina Pinotti; James L. Schwing; Albert Y. Zomaya (IPPS/SPDP, 1998)

A Fast Parallel Algorithm to Recognize P4-sparse Graphs. - Rong Lin; Stephan Olariu (Discret. Appl. Math., 1998)

A Novel Approach for CMOS Parallel Counter Design. - Rong Lin; Kevin E. Kerr; André S. Botha (EUROMICRO, 1999)

An Efficient VLSI Architecture Parallel Prefix Counting With Domino Logic. - Rong Lin; Koji Nakano; Stephan Olariu; Albert Y. Zomaya (IPPS/SPDP, 1999)

The Mesh with Hybrid Buses: An Efficient Parallel Architecture for Digital Geometry. - Rong Lin; Stephan Olariu; James L. Schwing; Biing-Feng Wang (IEEE Trans. Parallel Distributed Syst., 1999)

Efficient VLSI architectures for Columnsort. - Rong Lin; Stephan Olariu (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Reconfigurable Shift Switching Parallel Comparators. - Rong Lin; Stephan Olariu (VLSI Design, 1999)

Guest Editorial. - Stephan Olariu; Rong Lin (VLSI Design, 1999)

Parallel Multiplier Designs Utilizing A Non-Binary Logic Scheme. - Rong Lin (EUROMICRO, 2000)

A Non-binary Parallel Arithmetic Architecture. - Rong Lin; James L. Schwing (IPDPS Workshops, 2000)

A Reconfigurable Low-Power High-Performance Matrix Multiplier Design. - Rong Lin (ISQED, 2000)

Scalable Hardware-Algorithms for Binary Prefix Sums. - Rong Lin; Koji Nakano; Stephan Olariu; Maria Cristina Pinotti; James L. Schwing; Albert Y. Zomaya (IEEE Trans. Parallel Distributed Syst., 2000)

Inner Product Processor Designs Using High-Performance, Non-Binary Logic Circuits. - Rong Lin (PDCS, 2001)

A run-time reconfigurable array of multipliers architecture. - Rong Lin (IPDPS, 2001)

Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor Design. - Rong Lin (ISQED, 2001)

Reconfigurable parallel inner product processor architectures. - Rong Lin (IEEE Trans. Very Large Scale Integr. Syst., 2001)

A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits. - Rong Lin (VLSI Design, 2001)

Novel design and verification of a 16 x 16-b self-repairable reconfigurable inner product processor. - Rong Lin; Martin Margala (ACM Great Lakes Symposium on VLSI, 2002)

Bit-Matrix Decomposition and Dynamic Reconfiguration: A Unified Arithmetic Processor Architecture, Design and Test. - Rong Lin (IPDPS, 2002)

Fast Inner Product Computation on Short Buses. - Rong Lin; Stephan Olariu (VLSI Design, 2002)

A Reconfigurable Low-Power High-Performance Matrix Multiplier Architecture with Borrow Parallel Counters. - Rong Lin (IPDPS, 2003)

An Efficient Parallel Prefix Sums Architecture with Domino Logic. - Rong Lin; Koji Nakano; Stephan Olariu; Albert Y. Zomaya (IEEE Trans. Parallel Distributed Syst., 2003)

An Empirical Study on the Specification and Selection of Components Using Fuzzy Logic. - Kendra M. L. Cooper; João W. Cangussu; Rong Lin; Ganesan Sankaranarayanan; Ragouramane Soundararadjane; W. Eric Wong (CBSE, 2005)

Application research of the power line carrier communication multiband based on G3 technology. - Ping Hu; Shi Peng; Chengmin Wang; Huicong Fan; Rong Lin; Yong Liu (ICSAI, 2016)

Effects of Commensurability on the Friction and Energy Dissipation in Graphene/Graphene Interface. - Rong Lin; Zhiyong Wei; Yunfei Chen 004 (NEMS, 2020)

Contrastive Learning Framework by Maximizing Mutual Information for Visual Question Answering. - Rong Lin; Chun-Yang Zhang (SPAC, 2021)

Research on the precise employment model of college students from the perspective of competency. - Rong Lin (CIS, 2022)

Prediction of solar wind speed by applying convolutional neural network to potential field source surface (PFSS) magnetograms. - Rong Lin; Zhekai Luo; Jiansen He; Lun Xie; Chuanpeng Hou; Shuwei Chen (CoRR, 2023)

The differences in gastric cancer epidemiological data between SEER and GBD: a joinpoint and age-period-cohort analysis. - Zenghong Wu; Kun Zhang; Weijun Wang; Mengke Fan; Rong Lin (J. Big Data, 2024)