A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding. - Ya-Ting Shyu; Ying-Zu Lin; Rong-Sing Chu; Guan-Ying Huang; Soon-Jyh Chang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

An area- and power-efficient half-rate clock and data recovery circuit. - Yen-Long Lee; Soon-Jyh Chang; Rong-Sing Chu; Yen-Chi Chen; Jih Ren Goh; Chung-Ming Huang (ISCAS, 2014)