100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array. - Jingjing Wang; Rongjin Xu; Chixiao Chen; Fan Ye 001; Jun Xu 011; Junyan Ren (ASICON, 2015)

A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network. - Rongjin Xu; Yongzhen Chen; Mingshuo Wang; Ning Li 007; Fan Ye 001; Junyan Ren (ASICON, 2015)

A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer. - Dawei Ye; Rongjin Xu; Liangjian Lyu; Chuanjin Richard Shi (ISCAS, 2019)

A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm Sensitivity. - Dawei Ye; Rongjin Xu; Chuanjin Richard Shi (ISSCC, 2019)

A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification. - Yuting Tu; Rongjin Xu; Dawei Ye; Liangjian Lyu; Chuanjin Richard Shi (ISCAS, 2020)

A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission. - Liangjian Lyu; Dawei Ye; Rongjin Xu; Geng Mu; Heng Zhao; Yingfei Xiang; Yuting Tu; Yiyun Zhang; Chuanjin Richard Shi (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB In-Band Rejection to CW/AM Interference. - Dawei Ye; Yuting Tu; Wenjun Gong; Rongjin Xu; Chuanjin Richard Shi (A-SSCC, 2021)

A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain. - Dawei Ye; Rongjin Xu; Chuanjin Richard Shi (IEEE J. Solid State Circuits, 2021)

A 0.021mm2 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency. - Rongjin Xu; Dawei Ye; Sirou Li; Chuanjin Richard Shi (ISSCC, 2022)

A 2.0-2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction. - Rongjin Xu; Dawei Ye; Chuanjin Richard Shi (Integr., 2022)

Erratum to "A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain". - Dawei Ye; Rongjin Xu; Chuanjin Richard Shi (IEEE J. Solid State Circuits, 2022)

Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors. - Rongjin Xu; Dawei Ye; Chuanjin Richard Shi (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)