Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits. - Rongliang Fu; Zhimin Zhang 004; Guang-Ming Tang; Junying Huang; Xiaochun Ye; Dongrui Fan; Ninghui Sun (ACM Great Lakes Symposium on VLSI, 2020)

Equivalence Checking for Superconducting RSFQ Logic Circuits. - Rongliang Fu; Junying Huang; Zhimin Zhang 004 (ACM Great Lakes Symposium on VLSI, 2021)

A survey on superconducting computing technology: circuits, architectures and design tools. - Junying Huang; Rongliang Fu; Xiaochun Ye; Dongrui Fan (CCF Trans. High Perform. Comput., 2022)

JBNN: A Hardware Design for Binarized Neural Networks Using Single-Flux-Quantum Circuits. - Rongliang Fu; Junying Huang; Haibin Wu; Xiaochun Ye; Dongrui Fan; Tsung-Yi Ho (IEEE Trans. Computers, 2022)

A Global Optimization Algorithm for Buffer and Splitter Insertion in Adiabatic Quantum-Flux-Parametron Circuits. - Rongliang Fu; Mengmeng Wang 006; Yirong Kan; Nobuyuki Yoshikawa; Tsung-Yi Ho; Olivia Chen (ASP-DAC, 2023)

BOMIG: A Majority Logic Synthesis Framework for AQFP Logic. - Rongliang Fu; Junying Huang; Mengmeng Wang 006; Nobuyuki Yoshikawa; Bei Yu 001; Tsung-Yi Ho; Olivia Chen (DATE, 2023)

JRouter: A Multi-Terminal Hierarchical Length-Matching Router under Planar Manhattan Routing Model for RSFQ Circuits. - Xinda Chen; Rongliang Fu; Junying Huang; Huawei Cao; Zhimin Zhang 004; Xiaochun Ye; Tsung-Yi Ho; Dongrui Fan (ACM Great Lakes Symposium on VLSI, 2023)

Exact Logic Synthesis for Reversible Quantum-Flux-Parametron Logic. - Rongliang Fu; Olivia Chen; Nobuyuki Yoshikawa; Tsung-Yi Ho (ICCAD, 2023)

DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP Circuits. - Rongliang Fu; Olivia Chen; Bei Yu 001; Nobuyuki Yoshikawa; Tsung-Yi Ho (ICCAD, 2023)

RCGP: An Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits based on Efficient Cartesian Genetic Programming. - Rongliang Fu; Robert Wille; Tsung-Yi Ho (DAC, 2024)

JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum Circuits. - Siyan Chen; Rongliang Fu; Junying Huang; Zhimin Zhang 004; Xiaochun Ye; Tsung-Yi Ho; Dongrui Fan (DATE, 2024)

RABER: Reliability-Aware Bayesian-Optimization-based Control Layer Escape Routing for Flow-based Microfluidics. - Siyuan Liang; Rongliang Fu; Mengchu Li; Tsun-Ming Tseng; Ulf Schlichtmann; Tsung-Yi Ho (ICCAD, 2024)

FlatDD: A High-Performance Quantum Circuit Simulator using Decision Diagram and Flat Array. - Shui Jiang; Rongliang Fu; Lukas Burgholzer; Robert Wille; Tsung-Yi Ho; Tsung-Wei Huang (ICPP, 2024)

An Optimal DFF-Oriented Technology Legalization Algorithm for Rapid Single-Flux-Quantum Circuits. - Minglei Zhou; Rongliang Fu; Ran Zhang; Xiaochun Ye; Tsung-Yi Ho; Junying Huang (ACM Great Lakes Symposium on VLSI, 2025)

HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning. - Yuan Pu 001; Fangzhou Liu; Zhuolun He; Keren Zhu 001; Rongliang Fu; Ziyi Wang 010; Tsung-Yi Ho; Bei Yu 001 (ISPD, 2025)

Buffer and Splitter Insertion for Adiabatic Quantum-Flux-Parametron Circuits. - Rongliang Fu; Mengmeng Wang 006; Yirong Kan; Olivia Chen; Nobuyuki Yoshikawa; Bei Yu 001; Tsung-Yi Ho (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

TeMACLE: A Technology Mapping-Aware Area-Efficient Standard Cell Library Extension Framework. - Rongliang Fu; Chao Wang; Bei Yu 001; Tsung-Yi Ho (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Efficient Cartesian Genetic Programming-Based Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits. - Rongliang Fu; Robert Wille; Nobuyuki Yoshikawa; Tsung-Yi Ho (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)