Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits. - Rongtian Zhang; Kaushik Roy 001; Cheng-Kok Koh; David B. Janes (ICCAD, 2000)

Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration. - Rongtian Zhang; Kaushik Roy 001; Cheng-Kok Koh; David B. Janes (DAC, 2001)

Power trends and performance characterization of 3-dimensional integration. - Rongtian Zhang; Kaushik Roy 001; Cheng-Kok Koh; David B. Janes (ISCAS (4), 2001)

Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design. - Rongtian Zhang; Kaushik Roy 001; David B. Janes (ISLPED, 2001)

Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations. - Rongtian Zhang; Kaushik Roy 001; Cheng-Kok Koh; David B. Janes (ISQED, 2001)

Vertically integrated SOI circuits for low-power and high-performance applications. - Liqiong Wei; Rongtian Zhang; Kaushik Roy 001; Zhanping Chen; David B. Janes (IEEE Trans. Very Large Scale Integr. Syst., 2002)