6.3 A Heterogeneous 3D-IC consisting of two 28nm FPGA die and 32 reconfigurable high-performance data converters. - Christophe Erdmann; Donnacha Lowney; Adrian Lynam; Aidan Keady; John McGrath; Edward Cullen; Daire Breathnach; Denis Keane; Patrick Lynch; Marites De La Torre; Ronnie De La Torre; Peng Lim; et al. (ISSCC, 2014)

A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data Converters. - Christophe Erdmann; Donnacha Lowney; Adrian Lynam; Aidan Keady; John McGrath; Edward Cullen; Daire Breathnach; Denis Keane; Patrick Lynch; Marites De La Torre; Ronnie De La Torre; Peng Lim; et al. (IEEE J. Solid State Circuits, 2015)

16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC. - Bruno Vaz; Adrian Lynam; Bob Verbruggen; Asma Laraba; Conrado Mesadri; Ali Boumaalif; John McGrath; Umanath Kamath; Ronnie De La Torre; Alvin Manlapat; Daire Breathnach; Christophe Erdmann; et al. (ISSCC, 2017)

A modular 16NM Direct-RF TX/RX Embedding 9GS/S DAC and 4.5GS/S ADC with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic Integration in 5G Base-Station SoC. - Christophe Erdmann; Bob Verbruggen; Bruno Vaz; Roberto Pelliconi; John McGrath; Ryan Kinnerk; Ronnie De La Torre; John O'Dwyer; Patrick Lynch; Padraig Kelly; Peng Lim; Daire Breathnach; et al. (VLSI Circuits, 2018)

A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFET. - Bruno Vaz; Bob Verbruggen; Christophe Erdmann; Diarmuid Collins; John McGrath; Ali Boumaalif; Edward Cullen; Darragh Walsh; Alonso Morgado; Conrado Mesadri; Brian Long; Rajitha Pathepuram; et al. (VLSI Circuits, 2018)