IBM system z functional and performance verification using X-Gen. - Torsten Schober; Shimon Landa; Bodo Hoppe; Ronny Morad (HLDVT, 2008)

Special Session on Debugging. - Yoav Hollander; Alan J. Hu; João Lourenço; Ronny Morad (Haifa Verification Conference, 2010)

Ontology-Based Tools in the Service of Hardware Verification. - Eyal Bin; Alaa Ghanayim; Karen Holtz; Eitan Marcus; Ronny Morad; Ofer Peled; Michal Rimon; Gil Shurek; Elena Tsanko (SEKE, 2010)

Facing the challenge of new design features: an effective verification approach. - Wisam Kadry; Ronny Morad; Alex Goryachev; Eli Almog; Christopher A. Krygowski (DAC, 2011)

Checking architectural outputs instruction-by-instruction on acceleration platforms. - Debapriya Chatterjee; Anatoly Koyfman; Ronny Morad; Avi Ziv; Valeria Bertacco (DAC, 2012)

Accelerators and emulators: Can they become the platform of choice for hardware verification? - Bashir M. Al-Hashimi; Ronny Morad (DATE, 2012)

Approximating checkers for simulation acceleration. - Biruk Mammo; Debapriya Chatterjee; Dmitry Pidan; Amir Nahir; Avi Ziv; Ronny Morad; Valeria Bertacco (DATE, 2012)

SLAM: SLice And Merge - Effective Test Generation for Large Systems. - Tali Rabetti; Ronny Morad; Alex Goryachev; Wisam Kadry; Richard D. Peterson (Haifa Verification Conference, 2013)

Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms. - Debapriya Chatterjee; Biruk Mammo; Doowon Lee; Raviv Gal; Ronny Morad; Amir Nahir; Avi Ziv; Valeria Bertacco (ICCAD, 2013)

Panel: Future SoC verification methodology: UVM evolution or revolution? - Rolf Drechsler; Christophe Chevallaz; Franco Fummi; Alan J. Hu; Ronny Morad; Frank Schirrmeister; Alex Goryachev (DATE, 2014)

ArChiVED: Architectural checking via event digests for high performance validation. - Chang-Hong Hsu; Debapriya Chatterjee; Ronny Morad; Raviv Gal; Valeria Bertacco (DATE, 2014)

Solutions to IBM POWER8 verification challenges. - Klaus-Dieter Schubert; John M. Ludden; Salma Ayub; J. Behrend; Bishop Brock; Fady Copty; S. M. German; Oz Hershkovitz; H. Horbach; Jonathan R. Jackson; K. Keuerleber; J. Koesters; et al. (IBM J. Res. Dev., 2015)

Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification. - Doowon Lee; Tom Kolan; Arkadiy Morgenshtein; Vitali Sokhin; Ronny Morad; Avi Ziv; Valeria Bertacco (DAC, 2016)

Unveiling difficult bugs in address translation caching arrays for effective post-silicon validation. - George Papadimitriou 001; Dimitris Gizopoulos; Athanasios Chatzidimitriou; Tom Kolan; Anatoly Koyfman; Ronny Morad; Vitali Sokhin (ICCD, 2016)

ISA-independent post-silicon validation for the address translation mechanisms of modern microprocessors. - George Papadimitriou 001; Athanasios Chatzidimitriou; Dimitris Gizopoulos; Ronny Morad (IOLTS, 2016)

Cost-effective analysis of post-silicon functional coverage events. - Farimah Farahmandi; Ronny Morad; Avi Ziv; Ziv Nevo; Prabhat Mishra 001 (DATE, 2017)

Post-Silicon Validation in the SoC Era: A Tutorial Introduction. - Prabhat Mishra 001; Ronny Morad; Avi Ziv; Sandip Ray (IEEE Des. Test, 2017)