A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification. - Stéphan Jourdan; Ronny Ronen; Michael Bekerman; Bishara Shomar; Adi Yoaz (MICRO, 1998)

Correlated Load-Address Predictors. - Michael Bekerman; Stéphan Jourdan; Ronny Ronen; Gilad Kirshenboim; Lihu Rappoport; Adi Yoaz; Uri C. Weiser (ISCA, 1999)

Speculation Techniques for Improving Load Related Instruction Scheduling. - Adi Yoaz; Mattan Erez; Ronny Ronen; Stéphan Jourdan (ISCA, 1999)

eXtended Block Cache. - Stéphan Jourdan; Lihu Rappoport; Yoav Almog; Mattan Erez; Adi Yoaz; Ronny Ronen (HPCA, 2000)

Early load address resolution via register tracking. - Michael Bekerman; Adi Yoaz; Freddy Gabbay; Stéphan Jourdan; Maxim Kalaev; Ronny Ronen (ISCA, 2000)

Filtering Techniques to Improve Trace-Cache Efficiency. - Roni Rosner; Avi Mendelson; Ronny Ronen (IEEE PACT, 2001)

Coming challenges in microarchitecture and architecture. - Ronny Ronen; Avi Mendelson; Konrad Lai; Shih-Lien Lu; Fred J. Pollack; John Paul Shen (Proc. IEEE, 2001)

Dynamic techniques for load and load-use scheduling. - Amir Roth; Ronny Ronen; Avi Mendelson (Proc. IEEE, 2001)

Selecting long atomic traces for high coverage. - Roni Rosner; Micha Moffie; Yiannakis Sazeides; Ronny Ronen (ICS, 2003)

On Estimating Optimal Performance of CPU Dynamic Thermal Management. - Aviad Cohen 001; Lev Finkelstein; Avi Mendelson; Ronny Ronen; Dmitry Rudoy (IEEE Comput. Archit. Lett., 2003)

Micro-operation cache: a power aware frontend for variable instruction length ISA. - Baruch Solomon; Avi Mendelson; Ronny Ronen; Doron Orenstein; Yoav Almog (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Best of Both Latency and Throughput. - Ed Grochowski; Ronny Ronen; John Paul Shen; Hong Wang 003 (ICCD, 2004)

Guest Editors' Introduction: Micro's Top Picks from the Microarchitecture Conferences. - Ronny Ronen; Antonio González 001 (IEEE Micro, 2007)

DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals. - Amit Golander; Shlomo Weiss; Ronny Ronen (IEEE Comput. Archit. Lett., 2008)

Larrabee: a many-core Intel architecture for visual computing. - Ronny Ronen (Conf. Computing Frontiers, 2009)

Terascale chip multiprocessor memory hierarchy and programming model. - Shoumeng Yan; Xiaocheng Zhou; Ying Gao; Hu Chen; Sai Luo; Peinan Zhang; Naveen Cherukuri; Ronny Ronen; Bratin Saha (HiPC, 2009)

Programming model for a heterogeneous x86 platform. - Bratin Saha; Xiaocheng Zhou; Hu Chen; Ying Gao; Shoumeng Yan; Mohan Rajagopalan; Jesse Fang; Peinan Zhang; Ronny Ronen; Avi Mendelson (PLDI, 2009)

Synchronizing Redundant Cores in a Dynamic DMR Multicore Architecture. - Amit Golander; Shlomo Weiss; Ronny Ronen (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Improving the energy efficiency of Big Cores. - Kenneth Czechowski; Victor W. Lee; Ed Grochowski; Ronny Ronen; Ronak Singhal; Richard W. Vuduc; Pradeep Dubey (ISCA, 2014)

Why & When Deep Learning Works: Looking Inside Deep Learnings. - Ronny Ronen (CoRR, 2017)

Practical challenges in delivering the promises of real processing-in-memory machines. - Nishil Talati; Ameer Haj Ali; Rotem Ben Hur; Nimrod Wald; Ronny Ronen; Pierre-Emmanuel Gaillardon; Shahar Kvatinsky (DATE, 2018)

Not in Name Alone: A Memristive Memory Processing Unit for Real In-Memory Processing. - Ameer Haj Ali; Rotem Ben Hur; Nimrod Wald; Ronny Ronen; Shahar Kvatinsky (IEEE Micro, 2018)

IMAGING: In-Memory AlGorithms for Image processiNG. - Ameer Haj Ali; Rotem Ben Hur; Nimrod Wald; Ronny Ronen; Shahar Kvatinsky (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm. - Kunal Korgaonkar; Ronny Ronen; Anupam Chattopadhyay; Shahar Kvatinsky (CoRR, 2019)

CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM. - Nishil Talati; Heonjae Ha; Ben Perach; Ronny Ronen; Shahar Kvatinsky (IEEE Micro, 2019)

CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit. - Debjyoti Bhattacharjee; Anupam Chattopadhyay; Srijit Dutta; Ronny Ronen; Shahar Kvatinsky (ICCAD, 2020)

abstractPIM: Bridging the Gap Between Processing-In-Memory Technology and Instruction Set Architecture. - Adi Eliahu; Rotem Ben Hur; Ronny Ronen; Shahar Kvatinsky (VLSI-SOC, 2020)

abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory. - Adi Eliahu; Rotem Ben Hur; Ronny Ronen; Shahar Kvatinsky (VLSI-SoC (Selected Papers), 2020)

X-MAGIC: Enhancing PIM Using Input Overwriting Capabilities. - Natan Peled; Rotem Ben Hur; Ronny Ronen; Shahar Kvatinsky (VLSI-SOC, 2020)

SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput. - Rotem Ben Hur; Ronny Ronen; Ameer Haj Ali; Debjyoti Bhattacharjee; Adi Eliahu; Natan Peled; Shahar Kvatinsky (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory. - Orian Leitersdorf; Ben Perach; Ronny Ronen; Shahar Kvatinsky (DAC, 2021)

FiltPIM: In-Memory Filter for DNA Sequencing. - Marcel Khalifa; Rotem Ben Hur; Ronny Ronen; Orian Leitersdorf; Leonid Yavits; Shahar Kvatinsky (ICECS, 2021)

Making Memristive Processing-in-Memory Reliable. - Orian Leitersdorf; Ronny Ronen; Shahar Kvatinsky (ICECS, 2021)

multiPULPly: A Multiplication Engine for Accelerating Neural Networks on Ultra-low-power Architectures. - Adi Eliahu; Ronny Ronen; Pierre-Emmanuel Gaillardon; Shahar Kvatinsky (ACM J. Emerg. Technol. Comput. Syst., 2021)

MatPIM: Accelerating Matrix Operations with Memristive Stateful Logic. - Orian Leitersdorf; Ronny Ronen; Shahar Kvatinsky (ISCAS, 2022)

HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory. - Batel Oved; Orian Leitersdorf; Ronny Ronen; Shahar Kvatinsky (MOCAST, 2022)

Efficient Training of the Memristive Deep Belief Net Immune to Non-Idealities of the Synaptic Devices. - Wei Wang 209; Barak Hoffer; Tzofnat Greenberg-Toledo; Yang Li 203; Minhui Zou; Eric Herbelin; Ronny Ronen; Xiaoxin Xu; Yulin Zhao; Jianguo Yang; Shahar Kvatinsky (Adv. Intell. Syst., 2022)

PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics. - Ben Perach; Ronny Ronen; Benny Kimelfeld; Shahar Kvatinsky (CoRR, 2022)

PartitionPIM: Practical Memristive Partitions for Fast Processing-in-Memory. - Orian Leitersdorf; Ronny Ronen; Shahar Kvatinsky (CoRR, 2022)

The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems. - Ronny Ronen; Adi Eliahu; Orian Leitersdorf; Natan Peled; Kunal Korgaonkar; Anupam Chattopadhyay; Ben Perach; Shahar Kvatinsky (ACM J. Emerg. Technol. Comput. Syst., 2022)

MultPIM: Fast Stateful Multiplication for Processing-in-Memory. - Orian Leitersdorf; Ronny Ronen; Shahar Kvatinsky (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

On Consistency for Bulk-Bitwise Processing-in-Memory. - Ben Perach; Ronny Ronen; Shahar Kvatinsky (HPCA, 2023)

Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory. - Ben Perach; Ronny Ronen; Shahar Kvatinsky (NEWCAS, 2023)

Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory. - Ben Perach; Ronny Ronen; Shahar Kvatinsky (SOCC, 2023)

FourierPIM: High-Throughput In-Memory Fast Fourier Transform and Polynomial Multiplication. - Orian Leitersdorf; Yahav Boneh; Gonen Gazit; Ronny Ronen; Shahar Kvatinsky (CoRR, 2023)

ConvPIM: Evaluating Digital Processing-in-Memory through Convolutional Neural Network Acceleration. - Orian Leitersdorf; Ronny Ronen; Shahar Kvatinsky (CoRR, 2023)

CUDA-PIM: End-to-End Integration of Digital Processing-in-Memory from High-Level C++ to Microarchitectural Design. - Orian Leitersdorf; Ronny Ronen; Shahar Kvatinsky (CoRR, 2023)

AritPIM: High-Throughput In-Memory Arithmetic. - Orian Leitersdorf; Dean Leitersdorf; Jonathan Gal; Mor M. Dahan; Ronny Ronen; Shahar Kvatinsky (IEEE Trans. Emerg. Top. Comput., 2023)

PyPIM: Integrating Digital Processing-in-Memory from Microarchitectural Design to Python Tensors. - Orian Leitersdorf; Ronny Ronen; Shahar Kvatinsky (MICRO, 2024)

Accelerating DNA Read Mapping with Digital Processing-in-Memory. - Rotem Ben Hur; Orian Leitersdorf; Ronny Ronen; Lidor Goldshmidt; Idan Magram; Lior Kaplun; Leonid Yavitz; Shahar Kvatinsky (CoRR, 2024)

Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics. - Ben Perach; Ronny Ronen; Benny Kimelfeld; Shahar Kvatinsky (IEEE Trans. Emerg. Top. Comput., 2024)

Preprocessing Methods for Memristive Reservoir Computing for Image Recognition. - Rishona Daniels; Duna Wattad; Ronny Ronen; David Saad; Shahar Kvatinsky (CoRR, 2025)