Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS. - Rosa Rodríguez-Montañés; Jaume A. Segura 001; Víctor H. Champac; Joan Figueras; J. A. Rubio (ITC, 1991)

Bridging Defects Resistance Measurements in a CMOS Process. - Rosa Rodríguez-Montañés; Joan Figueras; Eric Bruls (ITC, 1992)

Quiescent current analysis and experimentation of defective CMOS circuits. - Jaume A. Segura 001; Víctor H. Champac; Rosa Rodríguez-Montañés; Joan Figueras; J. A. Rubio (J. Electron. Test., 1992)

Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability. - Rosa Rodríguez-Montañés; Joan Figueras (EDAC-ETC-EUROASIC, 1994)

Bridging defects resistance in the metal layer of a CMOS process. - Rosa Rodríguez-Montañés; E. M. J. G. Bruls; Joan Figueras (J. Electron. Test., 1996)

Bridges in sequential CMOS circuits: current-voltage signatur. - Rosa Rodríguez-Montañés; Joan Figueras (VTS, 1997)

Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs. - Rosa Rodríguez-Montañés; Joan Figueras (DATE, 1998)

IDDQ testing: state of the art and future trends. - Antoni Ferré; Eugeni Isern 001; Josep Rius 001; Rosa Rodríguez-Montañés; Joan Figueras (Integr., 1998)

RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. - Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001; Salvador Manich; Rosa Rodríguez-Montañés; Joan Figueras (ITC, 2002)

Resistance Characterization for Weak Open Defects. - Rosa Rodríguez-Montañés; Paul Volf; José Pineda de Gyvez (IEEE Des. Test Comput., 2002)

A Combinatorial Method for the Evaluation of Yield of Fault-Tolerant Systems-on-Chip. - Doru P. Munteanu; Víctor Suñé; Rosa Rodríguez-Montañés; Juan A. Carrasco (DSN, 2003)

Process-variability aware delay fault testing of ΔVT and weak-open defects. - Daniel Arumí-Delgado; Rosa Rodríguez-Montañés; José Pineda de Gyvez; Guido Gronthoud (ETW, 2003)

On the selection of efficient arithmetic additive test pattern generators [logic test]. - Salvador Manich; L. García; Luz Balado; Emili Lupon; Josep Rius 001; Rosa Rodríguez-Montañés; Joan Figueras (ETW, 2003)

Threshold Voltage Mismatch (DeltaVT) Fault Modeling. - José Pineda de Gyvez; Rosa Rodríguez-Montañés (VTS, 2003)

BIST Technique by Equally Spaced Test Vector Sequences. - Salvador Manich; L. García; Luz Balado; Emili Lupon; Josep Rius 001; Rosa Rodríguez-Montañés; Joan Figueras (VTS, 2004)

Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours. - Rosa Rodríguez-Montañés; D. Muñoz; Luz Balado; Joan Figueras (J. Electron. Test., 2004)

Defective behaviours of resistive opens in interconnect lines. - Daniel Arumí; Rosa Rodríguez-Montañés; Joan Figueras (ETS, 2005)

Lissajous Based Mixed-Signal Testing for N-Observable Signals. - Luz Balado; Emili Lupon; L. García; Rosa Rodríguez-Montañés; Joan Figueras (DDECS, 2006)

Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages. - Daniel Arumí; Rosa Rodríguez-Montañés; Joan Figueras; Stefan Eichenberger; Camelia Hora; Bram Kruseman; Maurice Lousberg; Ananta K. Majhi (VTS, 2007)

Diagnosis of Full Open Defects in Interconnecting Lines. - Rosa Rodríguez-Montañés; Daniel Arumí; Joan Figueras; Stefan Eichenberger; Camelia Hora; Bram Kruseman; Maurice Lousberg; Ananta K. Majhi (VTS, 2007)

Time-dependent Behaviour of Full Open Defects in Interconnect Lines. - Rosa Rodríguez-Montañés; Daniel Arumí; Joan Figueras; Stefan Eichenberger; Camelia Hora; Bram Kruseman (ITC, 2008)

Full Open Defects in Nanometric CMOS. - Daniel Arumí; Rosa Rodríguez-Montañés; Joan Figueras; Stefan Eichenberger; Camelia Hora; Bram Kruseman (VTS, 2008)

Experimental Characterization of CMOS Interconnect Open Defects. - Daniel Arumí; Rosa Rodríguez-Montañés; Joan Figueras (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Delay caused by resistive opens in interconnecting lines. - Daniel Arumí; Rosa Rodríguez-Montañés; Joan Figueras (Integr., 2009)

Diagnosis of full open defects in interconnect lines with fan-out. - Rosa Rodríguez-Montañés; Daniel Arumí; Joan Figueras; Stefan Eichenberger; Camelia Hora; Bram Kruseman (ETS, 2010)

Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out. - Daniel Arumí; Rosa Rodríguez-Montañés; Joan Figueras; Stefan Eichenberger; Camelia Hora; Bram Kruseman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Gate Leakage Impact on Full Open Defects in Interconnect Lines. - Daniel Arumí; Rosa Rodríguez-Montañés; Joan Figueras; Stefan Eichenberger; Camelia Hora; Bram Kruseman (IEEE Trans. Very Large Scale Integr. Syst., 2011)

BIST architecture to detect defects in tsvs during pre-bond testing. - Daniel Arumí; Rosa Rodríguez-Montañés; Joan Figueras (ETS, 2013)

Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents. - Daniel Arumí; Rosa Rodríguez-Montañés; Joan Figueras; Stefan Eichenberger; Camelia Hora; Bram Kruseman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Reliability estimation at block-level granularity of spin-transfer-torque MRAMs. - Stefano Di Carlo; Marco Indaco; Paolo Prinetto; Elena I. Vatajelu; Rosa Rodríguez-Montañés; Joan Figueras (DFT, 2014)

Post-bond test of Through-Silicon Vias with open defects. - Rosa Rodríguez-Montañés; Daniel Arumí; Joan Figueras (ETS, 2014)

Pre-bond testing of weak defects in TSVs. - Daniel Arumí; Rosa Rodríguez-Montañés; Joan Figueras (IOLTS, 2014)

Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell. - Elena I. Vatajelu; Rosa Rodríguez-Montañés; Marco Indaco; Michel Renovell; Paolo Prinetto; Joan Figueras (DATE, 2015)

STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations. - Elena I. Vatajelu; Rosa Rodríguez-Montañés; Marco Indaco; Paolo Prinetto; Joan Figueras (DTIS, 2015)

Power-aware voltage tuning for STT-MRAM reliability. - Elena I. Vatajelu; Rosa Rodríguez-Montañés; Stefano Di Carlo; Marco Indaco; Michel Renovell; Paolo Prinetto; Joan Figueras (ETS, 2015)

RRAM based cell for hardware security applications. - Daniel Arumí; Salvador Manich; Rosa Rodríguez-Montañés (IVSW, 2016)

Prebond Testing of Weak Defects in TSVs. - Daniel Arumí; Rosa Rodríguez-Montañés; Joan Figueras (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents. - Daniel Arumí; Rosa Rodríguez-Montañés; Joan Figueras (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Mitigating read & write errors in STT-MRAM memories under DVS. - Elena-Ioana Vatajelu; Rosa Rodríguez-Montañés; Michel Renovell; Joan Figueras (ETS, 2017)

The Low Area Probing Detector as a Countermeasure Against Invasive Attacks. - Michael Weiner 004; Salvador Manich; Rosa Rodríguez-Montañés; Georg Sigl (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Postbond Test of Through-Silicon Vias With Resistive Open Defects. - Rosa Rodríguez-Montañés; Daniel Arumí; Joan Figueras (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Low Cost AES Protection Against DPA Using Rolling Codes. - P. Albiol; Salvador Manich; Daniel Arumí; Rosa Rodríguez-Montañés; Álvaro Gómez-Pau (DCIS, 2021)

Simulation of serial RRAM cell based on a Verilog-A compact model. - Binbin Yang; Daniel Arumí; Salvador Manich; Álvaro Gómez-Pau; Rosa Rodríguez-Montañés; Juan Bautista Roldán; Mireia Bargallo González; Francesca Campabadal; Liang Fang (DCIS, 2021)

On the Fitting and Improvement of RRAM Stanford-Based Model Parameters Using TiN/Ti/HfO2/W Experimental Data. - V. Mahboubi; Daniel Arumí; Álvaro Gómez-Pau; Rosa Rodríguez-Montañés; Salvador Manich (DCIS, 2022)

True Random Number Generator Based on the Variability of the High Resistance State of RRAMs. - Maryam Akbari; Sattar Mirzakuchaki; Daniel Arumí; Salvador Manich; Álvaro Gómez-Pau; Francesca Campabadal; Mireia Bargallo González; Rosa Rodríguez-Montañés (IEEE Access, 2023)