Architectures matérielles pour l'arithmétique stochastique discrète. (Hardware architecture for discrete stochastic arithmetic). - Roselyne Chotin-Avot (2003)

Hardware Implementation of Discrete Stochastic Arithmetic. - Roselyne Avot-Chotin; Habib Mehrez (Numer. Algorithms, 2004)

MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation. - Alain Greiner; Frédéric Pétrot; M. Carrier; Mounir Benabdenbi; Roselyne Chotin-Avot; Raphaël Labayrade (ReCoSoC, 2006)

Arithmetic Data Path Optimization Using Borrow-Save Representation. - Sophie Belloeil; Roselyne Chotin-Avot; Habib Mehrez (ISVLSI, 2008)

Stratus: Free design of highly parametrized VLSI modules interoperable with commercial tools. - Sophie Belloeil-Dupuis; Roselyne Chotin-Avot; Habib Mehrez (ISQED, 2011)

Efficient parallel-pipelined GHASH for message authentication. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (ReConFig, 2012)

A defect-tolerant cluster in a mesh SRAM-based FPGA. - Arwa Ben Dhia; Saif-Ur Rehman; Adrien Blanchardon; Lirida A. B. Naviner; Mounir Benabdenbi; Roselyne Chotin-Avot; Emna Amouri; Habib Mehrez; Zied Marrakchi (FPT, 2013)

Efficient AES-GCM for VPNs using FPGAs. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (MWSCAS, 2013)

Efficient state-dependent power model for multi-bit flip-flop banks. - Jung Kyu Chae; Severine Bertrand; Pierre-Francois Ollagnon; Paul Mougeat; Jean-Arnaud Francois; Roselyne Chotin-Avot; Habib Mehrez (MWSCAS, 2013)

Protecting FPGA bitstreams using authenticated encryption. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (NEWCAS, 2013)

Lightweight and compact solutions for secure reconfiguration of FPGAs. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (ReConFig, 2013)

Improved method for parallel AES-GCM cores using FPGAs. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (ReConFig, 2013)

Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture. - Emna Amouri; Adrien Blanchardon; Roselyne Chotin-Avot; Habib Mehrez; Zied Marrakchi (ReConFig, 2013)

A formalism of the specifications for library development. - Jung Kyu Chae; Paul Mougeat; Jean-Arnaud Francois; Roselyne Chotin-Avot; Habib Mehrez (SoCC, 2013)

High speed authenticated encryption for slow changing key applications using reconfigurable devices. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (Wireless Days, 2013)

Exploring redundant arithmetics in computer-aided design of arithmetic datapaths. - Sophie Belloeil-Dupuis; Roselyne Chotin-Avot; Habib Mehrez (Integr., 2013)

FPGA-Based High Performance AES-GCM Using Efficient Karatsuba Ofman Algorithm. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (ARC, 2014)

Towards high performance GHASH for pipelined AES-GCM using FPGAs (abstract only). - Karim M. Abdellatif; Roselyne Chotin-Avot; Zied Marrakchi; Habib Mehrez; Qingshan Tang (FPGA, 2014)

Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy. - Adrien Blanchardon; Roselyne Chotin-Avot; Habib Mehrez; Emna Amouri (FPL, 2014)

Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA. - Saif-Ur Rehman; Adrien Blanchardon; Arwa Ben Dhia; Mounir Benabdenbi; Roselyne Chotin-Avot; Lirida A. B. Naviner; Lorena Anghel; Habib Mehrez; Emna Amouri; Zied Marrakchi (ISVLSI, 2014)

A reference-based specification tool for creating reliable library development specifications. - Jung Kyu Chae; Paul Mougeat; Jean-Arnaud Francois; Roselyne Chotin-Avot; Habib Mehrez (NEWCAS, 2014)

Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA. - Adrien Blanchardon; Roselyne Chotin-Avot; Habib Mehrez; Emna Amouri (ReConFig, 2014)

Low cost solutions for secure remote reconfiguration of FPGAs. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (Int. J. Embed. Syst., 2014)

Authenticated encryption on FPGAs from the static part to the reconfigurable part. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (Microprocess. Microsystems, 2014)

Using Timing-Driven Inter-FPGA Routing for Multi-FPGA Prototyping Exploration. - Umer Farooq 001; Roselyne Chotin-Avot; Muhammad Moazam Azeem; Zouha Cherif; Maminionja Ravoson; Saqib Khan; Habib Mehrez (DSD, 2016)

AEGIS-Based Efficient Solution for Secure Reconfiguration of FPGAs. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (CS2@HiPEAC, 2016)

Multiple FPGAs based prototyping and debugging with complete design flow. - Muhammad Moazam Azeem; Roselyne Chotin-Avot; Umer Farooq 001; Maminionja Ravoson; Habib Mehrez (IDT, 2016)

Inter-FPGA routing environment for performance exploration of multi-FPGA systems. - Umer Farooq 001; Roselyne Chotin-Avot; Muhammad Moazam Azeem; Maminionja Ravoson; Mariem Turki; Habib Mehrez (RSP, 2016)

AES-GCM and AEGIS: Efficient and High Speed Hardware Implementations. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (J. Signal Process. Syst., 2017)

Novel architectural space exploration environment for multi-FPGA based prototyping systems. - Umer Farooq 001; Roselyne Chotin-Avot; Muhammad Moazam Azeem; Maminionja Ravoson; Habib Mehrez (Microprocess. Microsystems, 2018)

MixLock: Securing Mixed-Signal Circuits via Logic Locking. - Julian Leonhard; Muhammad Yasin; Shadi Turk; Mohammed Thari Nabeel; Marie-Minerve Louërat; Roselyne Chotin-Avot; Hassan Aboushady; Ozgur Sinanoglu; Haralampos-G. D. Stratigopoulos (DATE, 2019)