RISC-V Online Tutor. - Fearghal Morgan; Arthur Beretta; Ian Gallivan; Joseph Clancy; Frédéric Rousseau 001; Roshan George; László Bakó; Frank Callaly (REV, 2021)

HDLGen-ChatGPT Case Study: RISC-V Processor VHDL and Verilog Model - Testbench and EDA Project Generation. - Fearghal Morgan; John Patrick Byrne; Abishek Bupathi; Roshan George; Muhammad Adnan Elahi; Frank Callaly; Sean Kelly; Declan O'Loughlin (RSP, 2023)