Crosstalk immune interconnect driver design. - Roshan Weerasekera; Li-Rong Zheng 001; Dinesh Pamunuwa; Hannu Tenhunen (SoC, 2004)

Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses. - Roshan Weerasekera; Li-Rong Zheng 001; Dinesh Pamunuwa; Hannu Tenhunen (PATMOS, 2005)

Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. - Roshan Weerasekera; Dinesh Pamunuwa; Li-Rong Zheng 001; Hannu Tenhunen (SLIP, 2006)

Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. - Roshan Weerasekera; Li-Rong Zheng 001; Dinesh Pamunuwa; Hannu Tenhunen (ICCAD, 2007)

Early selection of system implementation choice among SoC, SoP and 3-D Integration. - Roshan Weerasekera; Li-Rong Zheng 001; Dinesh Pamunuwa; Hannu Tenhunen (SoCC, 2007)

Delay-Balanced Smart Repeaters for On-Chip Global Signaling. - Roshan Weerasekera; Dinesh Pamunuwa; Li-Rong Zheng 001; Hannu Tenhunen (VLSI Design, 2007)

Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime. - Roshan Weerasekera; Dinesh Pamunuwa; Li-Rong Zheng 001; Hannu Tenhunen (IEEE Trans. Very Large Scale Integr. Syst., 2008)

System Interconnection Design Trade-offs in Three-Dimensional (3-D) Integrated Circuits. - Roshan Weerasekera (2008)

Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh. - Matt Grange; Awet Yemane Weldezion; Dinesh Pamunuwa; Roshan Weerasekera; Zhonghai Lu; Axel Jantsch; Dave Shippen (3DIC, 2009)

Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits. - Roshan Weerasekera; Matt Grange; Dinesh Pamunuwa; Hannu Tenhunen; Li-Rong Zheng 001 (3DIC, 2009)

3-D memory organization and performance analysis for multi-processor network-on-chip architecture. - Awet Yemane Weldezion; Zhonghai Lu; Roshan Weerasekera; Hannu Tenhunen (3DIC, 2009)

Scalability of network-on-chip communication architecture for 3-D meshes. - Awet Yemane Weldezion; Matt Grange; Dinesh Pamunuwa; Zhonghai Lu; Axel Jantsch; Roshan Weerasekera; Hannu Tenhunen (NOCS, 2009)

Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints. - Roshan Weerasekera; Dinesh Pamunuwa; Li-Rong Zheng 001; Hannu Tenhunen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits. - Roshan Weerasekera; Matt Grange; Dinesh Pamunuwa; Hannu Tenhunen (DATE, 2010)

Interconnect design and analysis for Through Silicon Interposers (TSIs). - Joseph Romen Cubillo; Roshan Weerasekera; Zaw Zaw Oo; En-Xiao Liu; Bob Conn; Surya Bhattacharya; Robert Patti (3DIC, 2011)

Design exploration of 3D stacked non-volatile memory by conductive bridge based crossbar. - Yuhao Wang 002; Chun Zhang; Revanth Nadipalli; Hao Yu 001; Roshan Weerasekera (3DIC, 2011)

Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning. - Matthew Grange; Axel Jantsch; Roshan Weerasekera; Dinesh Pamunuwa (ICCAD, 2011)

Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks. - Matt Grange; Roshan Weerasekera; Dinesh Pamunuwa; Axel Jantsch; Awet Yemane Weldezion (NOCS, 2011)

3-D integration and the limits of silicon computation. - Dinesh Pamunuwa; Matthew Grange; Roshan Weerasekera; Axel Jantsch (VLSI-SoC, 2011)

High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer. - Jiacheng Wang 001; Shunli Ma; Sai Manoj Pudukotai Dinakarrao; Mingbin Yu; Roshan Weerasekera; Hao Yu 001 (3DIC, 2013)

Fabrication and Assembly of Cu-RDL-Based 2.5-D Low-Cost Through Silicon Interposer (LC-TSI). - Guruprasad Katti; S. W. Ho; Li Hong Yu; Songbai Zhang; Rahul Dutta; Roshan Weerasekera; Ka-Fai Chang; Jong-Kai Lin; Srinivasa Rao Vempati; Surya Bhattacharya (IEEE Des. Test, 2015)

BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems. - Chao Wang 016; Jun Zhou 017; Roshan Weerasekera; Bin Zhao; Xin Liu 015; Philippe Royannez; Minkyu Je (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Excitable London: Street map analysis with Oregonator model. - Andrew Adamatzky; Neil Phillips; Roshan Weerasekera; Michail-Antisthenis I. Tsompanas; Georgios Ch. Sirakoulis (CoRR, 2018)

Neuromorphic Liquid Marbles With Aqueous Carbon Nanotube Cores. - Richard Mayne; Thomas C. Draper; Neil Phillips; James Gerald Holland Whiting; Roshan Weerasekera; Claire Fullarton; Ben P. J. de Lacy Costello; Andrew Adamatzky (CoRR, 2019)

Electrical Signal Transfer by Fungi. - Neil Phillips; Roshan Weerasekera; Nic Roberts; Andrew Adamatzky (Fungal Machines, 2023)

Propagation of electrical signals by fungi. - Richard Mayne; Nic Roberts; Neil Phillips; Roshan Weerasekera; Andrew Adamatzky (Biosyst., 2023)

Machine Learning Assisted Postural Movement Recognition using Photoplethysmography(PPG). - Robbie Maccay; Roshan Weerasekera (CoRR, 2024)

Incident and Load Power Relations in a Mismatched Lossless Transmission Line. - Disala Uduwawala; Roshan Weerasekera (Circuits Syst. Signal Process., 2024)

Nanoelectromechanical Binary Comparator for Edge-Computing Applications. - Victor Marot; Manu Bala Krishnan; Mukesh Kumar Kulsreshath; Elliott Worsey; Roshan Weerasekera; Dinesh Pamunuwa (DATE, 2025)

DT2HDL: A Binary Decision Tree to HDL Generation Tool. - Qijia Tang; Dinesh Pamunuwa; Roshan Weerasekera (ISQED, 2025)