Automatic generation of a parallel tile processing unit for algorithms with non-affine array references. - Rosilde Corvino; Stéphane Mancini; Roberto Guizzetti (IFMT, 2008)

Design Space Exploration for data-dominated image applications with non-affine array references. (Exploration de l'espace des architectures pour des systèmes de traitement d'image, analyse faite sur des blocs fondamentaux de la rétine numérique). - Rosilde Corvino (2009)

Architecture Exploration for Efficient Data Transfer and Storage in Data-Parallel Applications. - Rosilde Corvino; Abdoulaye Gamatié; Pierre Boulet (Euro-Par (1), 2010)

Transformation-Based Exploration of Data Parallel Architecture for Customizable Hardware: A JPEG Encoder Case Study. - Rosilde Corvino; Erkan Diken; Abdoulaye Gamatié; Lech Józwiak (DSD, 2012)

Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW Processors. - Roel Jordans; Rosilde Corvino; Lech Józwiak (DSD, 2012)

ASAM: Automatic Architecture Synthesis and Application Mapping. - Lech Józwiak; Menno Lindwer; Rosilde Corvino; Paolo Meloni; Laura Micconi; Jan Madsen; Erkan Diken; Deepak Gangadharan; Roel Jordans; Sebastiano Pomata; Paul Pop; Giuseppe Tuveri; et al. (DSD, 2012)

Abstract Clocks for the DSE of Data-Intensive Applications on MPSoCs. - Rosilde Corvino; Abdoulaye Gamatié (ISPA, 2012)

Design space exploration in application-specific hardware synthesis for multiple communicating nested loops. - Rosilde Corvino; Abdoulaye Gamatié; Marc Geilen; Lech Józwiak (ICSAMOS, 2012)

Exploring processor parallelism: Estimation methods and optimization strategies. - Roel Jordans; Rosilde Corvino; Lech Józwiak; Henk Corporaal (DDECS, 2013)

An Efficient Method for Energy Estimation of Application Specific Instruction-Set Processors. - Roel Jordans; Rosilde Corvino; Lech Józwiak; Henk Corporaal (DSD, 2013)

Rapid and accurate energy estimation of vector processing in VLIW ASIPs. - Erkan Diken; Rosilde Corvino; Lech Józwiak (MECO, 2013)

Instruction-set architecture exploration strategies for deeply clustered VLIW ASIPs. - Roel Jordans; Rosilde Corvino; Lech Józwiak; Henk Corporaal (MECO, 2013)

Hierarchical DSE for multi-ASIP platforms. - Laura Micconi; Rosilde Corvino; Deepak Gangadharan; Jan Madsen; Paul Pop; Lech Józwiak (MECO, 2013)

ASAM: Automatic architecture synthesis and application mapping. - Lech Józwiak; Menno Lindwer; Rosilde Corvino; Paolo Meloni; Laura Micconi; Jan Madsen; Erkan Diken; Deepak Gangadharan; Roel Jordans; Sebastiano Pomata; Paul Pop; Giuseppe Tuveri; et al. (Microprocess. Microsystems, 2013)

Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths. - Erkan Diken; Roel Jordans; Rosilde Corvino; Lech Józwiak; Henk Corporaal; Felipe Augusto Chies (Microprocess. Microsystems, 2014)

Automatic instruction-set architecture synthesis for VLIW processor cores in the ASAM project. - Roel Jordans; Lech Józwiak; Henk Corporaal; Rosilde Corvino (Microprocess. Microsystems, 2017)

Extending Halide to Improve Software Development for Imaging DSPs. - Sander Vocke; Henk Corporaal; Roel Jordans; Rosilde Corvino; Rick J. M. Nas (ACM Trans. Archit. Code Optim., 2017)

Concrete Syntax Metapatterns. - Luka Miljak; Casper Bach Poulsen; Rosilde Corvino (SLE, 2024)

Custom static analysis to enhance insight into the usage of in-house libraries. - Piërre van de Laar; Rosilde Corvino; Arjan J. Mooij; Hans van Wezep; Raymond Rosmalen (J. Syst. Softw., 2024)