A multigigabit backplane transceiver core in 0.13-μm CMOS with a power-efficient equalization architecture. - Kannan Krishna; David A. Yokoyama-Martin; Aaron Caffee; Chris Jones; Mat Loikkanen; James Parker; Ross Segelken; Jeff L. Sonntag; John T. Stonick; Steve Titus; Daniel Weinlader; Skye Wolfer (IEEE J. Solid State Circuits, 2005)

A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS. - David A. Yokoyama-Martin; Kannan Krishna; John T. Stonick; Aaron Caffee; E. K. Gamble; Chris Jones; J. Mcneal; James Parker; Ross Segelken; Jeff L. Sonntag; K. Umino; J. Upton; et al. (CICC, 2006)