Offset word-line architecture for scaling DRAMs to the gigabit level. - Roy E. Scheuerlein; James D. Meindl (IEEE J. Solid State Circuits, 1988)

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing. - Nicky Chau-Chun Lu; Gary B. Bronner; Koji Kitamura; Roy E. Scheuerlein; Walter H. Henkels; Sang H. Dhong; Yasunao Katayama; Toshiaki Kirihata; Hideto Niijima; Robert L. Franch; Wei Wang; Motoo Nishiwaki; et al. (IEEE J. Solid State Circuits, 1989)

A pulsed sensing scheme with a limited bit-line swing. - Roy E. Scheuerlein; Yasunao Katayama; Toshiaki Kirihata; Yoshinori Sakaue; Akashi Satoh; Toshio Sunaga; T. Yoshikawa; Koji Kitamura; Sang H. Dhong (IEEE J. Solid State Circuits, 1992)

A large VDS data retention test pattern for DRAM's. - Robert L. Franch; Sang H. Dhong; Roy E. Scheuerlein (IEEE J. Solid State Circuits, 1992)

A 14-ns 14-Mb CMOS DRAM with 300-mW active power. - Toshiaki Kirihata; Sang H. Dhong; Koji Kitamura; Toshio Sunaga; Yasunao Katayama; Roy E. Scheuerlein; Akashi Satoh; Yoshinori Sakaue; Kentaroh Tobimatsu; Koji Hosokawa; Takaki Saitoh; Takefumi Yoshikawa; et al. (IEEE J. Solid State Circuits, 1992)