A 1.8/2.4-ghz dualband cmos low noise amplifier using miller capacitance tuning. - Depak Balemarthy; Roy Paily (ISLPED, 2008)

Impact of Bias Voltage on Magnetic Inductance of Carbon Nanotube Interconnects. - K. C. Narasimhamurthy; Roy P. Paily (VLSI Design, 2009)

Design of QRS Detection and Heart Rate Estimation System on FPGA. - Sudheer Kurakula; A. S. D. P. Sudhansh; Roy Paily; Samarendra Dandapat (ACC (4), 2011)

Performance Comparison of Thin-Film Transistors Fabricated Using Different Purity Semiconducting Nanotubes. - K. C. Narasimhamurthy; Roy P. Paily (VLSI Design, 2011)

Fabrication and characterisation of high-performance and high-current back-gate thin-film field-effect transistors using sorted single-walled carbon nanotubes. - K. C. Narasimhamurthy; Roy P. Paily (IET Circuits Devices Syst., 2011)

Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding. - Rahul Shrestha; Roy P. Paily (VDAT, 2012)

Low power 2.4 GHz RF transmitter for satellite subsystem using CORDIC based frequency translator. - Amrita Brahmachari; Roy P. Paily (WOCN, 2012)

Fpga Implementation of High Speed and Low Power Architectures for Image Segmentation using Sobel Operators. - Abdul Raouf Khalid; Roy Paily (J. Circuits Syst. Comput., 2012)

Resonant Frequency Characteristics of a SAW Device Attached to Resonating Micropillars. - N. Ramakrishnan; Harshal B. Nemade; Roy Paily Palathinkal (Sensors, 2012)

A novel state metric normalization technique for high-throughput maximum-a-posteriori-probability decoder. - Rahul Shrestha; Roy P. Paily (ICACCI, 2013)

A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance. - Ratul Kumar Baruah; Roy P. Paily (VDAT, 2013)

An Ultra-Wideband Baseband Transmitter Design for Wireless Body Area Network. - R. K. Naga Mahesh; Akash Ganesan; Manchi Pavan Kumar; Roy Paily (VDAT, 2013)

Gain, NF and IIP3 Budgeting of LTE Receiver Front End. - Vinay M. M.; Roy Paily; Anil Mahanta (VLSI Design, 2013)

Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding. - Rahul Shrestha; Roy P. Paily (VLSI Design, 2013)

Performance and throughput analysis of turbo decoder for the physical layer of digitalvideo-broadcasting-satellite-services-tohandhelds standard. - Rahul Shrestha; Roy P. Paily (IET Commun., 2013)

Hardware Implementation and Testing of Log-MAPP Decoder Based on Novel Un-grouped Sliding-Window Technique. - Rahul Shrestha; Roy Paily (ISED, 2014)

An efficient hardware architecture for stereo disparity estimation. - Fradaric Joseph; Kiran Francis; Archita Hore; Siddhanta Roy; S. Josephine; Roy P. Paily (VDAT, 2014)

Fabrication and Testing of an Osmotic Pressure Sensor for Glucose Sensing Application. - Nagesh Ch; Roy P. Paily (Micromachines, 2014)

High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards. - Rahul Shrestha; Roy P. Paily (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Distributed Arithmetic based Split-Radix FFT. - Sunil P. Joshi; Roy Paily (J. Signal Process. Syst., 2014)

A low-power subthreshold LNA for mobile applications. - Vinay M. M.; Roy P. Paily; Anil Mahanta (VDAT, 2015)

An efficient on-chip energy processing circuit for micro-scale energy harvesting systems. - Saroj Mondal; Roy P. Paily (VDAT, 2015)

VLSI Design and Hardware Implementation of High-Speed Energy-Efficient Logarithmic-MAP Decoder. - Rahul Shrestha; Roy P. Paily (J. Low Power Electron., 2015)

High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule. - Sachin Kumawat; Rahul Shrestha; Nikunj Daga; Roy P. Paily (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A New PVT Compensation Technique Based on Current Comparison for Low-Voltage, Near Sub-Threshold LNA. - Vinaya M. M.; Roy P. Paily; Anil Mahanta (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Comparative Study of Simplified MAP Algorithms and an Implementation of Non-Parallel-Radix-2 Turbo Decoder. - Rahul Shrestha; Roy P. Paily (J. Signal Process. Syst., 2015)

Design and Implementation of Low-Power Digital Baseband Transceivers for IEEE802.15.6 Standard. - Manchi Pavan Kumar; Roy Paily; Anup Kumar Gogoi (VLSID, 2016)

Power Optimization of LNA for LTE Receiver. - Vinaya M. M.; Roy Paily; Anil Mahanta (VLSID, 2016)

An Efficient on Chip Power Management Architecture for Solar Energy Harvesting Systems. - Saroj Mondal; Roy P. Paily (VLSID, 2016)

Design and Implementation of Blind Assistance System Using Real Time Stereo Vision Algorithms. - Vaddi Chandra Sekhar; Satyajit Bora; Monalisa Dash; Manchi Pavan Kumar; S. Josephine; Roy Paily (VLSID, 2016)

Memory-Reduced Maximum A Posteriori Probability Decoding for High-Throughput Parallel Turbo Decoders. - Rahul Shrestha; Roy Paily (Circuits Syst. Signal Process., 2016)

Multi-standard high-throughput and low-power quasi-cyclic low density parity check decoder for worldwide interoperability for microwave access and wireless fidelity standards. - Vijaya Kumar Kanchetla; Rahul Shrestha; Roy Paily (IET Circuits Devices Syst., 2016)

Analysis and design of moderate inversion based low power low-noise amplifier. - Vinaya M. M.; Roy Paily; Anil Mahanta (IET Comput. Digit. Tech., 2016)

An Efficient On-Chip Switched-Capacitor-Based Power Converter for a Microscale Energy Transducer. - Saroj Mondal; Roy P. Paily (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

On-Chip Photovoltaic Power Harvesting System With Low-Overhead Adaptive MPPT for IoT Nodes. - Saroj Mondal; Roy Paily (IEEE Internet Things J., 2017)

Efficient Solar Power Management System for Self-Powered IoT Node. - Saroj Mondal; Roy Paily (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Low-Power Digital Baseband Transceiver Design for UWB Physical Layer of IEEE 802.15.6 Standard. - Manchi Pavan Kumar; Roy Paily; Anup Kumar Gogoi (IEEE Trans. Ind. Informatics, 2017)

Analysis of Electromagnetic Actuation System for Different Coil Topologies. - Pralay Chakrabarty; Siddhanta Roy; Roy Paily (TENCON, 2019)

Low Power 10T SRAM Cell with Improved Stability Solving Soft Error Issue. - Rohit Lorenzo; Roy Paily (TENCON, 2019)

Fabrication of Back to Back Schottky Micro-Diodes Using Silver Nanoparticle Film and Zinc Oxide Nanowire Mat for Biological Interactions. - Vimal Kumar Singh Yadav; Siddhanta Roy; Gayatri Natu; Roy Paily (TENCON, 2019)

An Efficient Architecture for QRS Detection in FPGA Using Integer Haar Wavelet Transform. - Soham Talukder; Rajan Singh; Satyajit Bora; Roy Paily (Circuits Syst. Signal Process., 2020)

A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications. - Satyajit Bora; Roy Paily (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Design and Implementation of Adaptive Binary Divider for Fixed-Point and Floating-Point Numbers. - Satyajit Bora; Roy Paily (Circuits Syst. Signal Process., 2022)

Half-selection disturbance free 8T low leakage SRAM cell. - Rohit Lorenzo; Roy Paily (Int. J. Circuit Theory Appl., 2022)

Securing AES Designs Against Power Analysis Attacks: A Survey. - Thockchom Birjit Singha; Roy Paily Palathinkal; Shaik Rafi Ahamed (IEEE Internet Things J., 2023)

Impact of Pipelining on Low Power IoT applicable RISC-V ISA Core Micro-architectures. - Titu Mary Ignatius; Satyajit Bora; Roy Paily Palathinkal (MCSoC, 2024)

Power Side-Channel Attacks on Crypto-Core Based on RISC-V ISA for High-Security Applications. - Titu Mary Ignatius; Thockchom Birjit Singha; Roy Paily Palathinkal (IEEE Access, 2024)

Improvement in Resilience of AES Design With Reconfigured CFB Mode Against Power Attacks. - Thockchom Birjit Singha; Basa Sanjana; Titu Mary Ignatius; Roy Paily Palathinkal; Shaik Rafi Ahamed (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Analysis of S-Box Hardware Resources to Improve AES Intrinsic Security Against Power Attacks. - Thockchom Birjit Singha; Roy Paily Palathinkal; Shaik Rafi Ahamed (IEEE Embed. Syst. Lett., 2024)

Low Form-Factor Switchless Dual-Band Matching Network for RF Power Harvesting Systems. - Arun Mohan 001; Saroj Mondal; Yash N. Rayudu; Roy P. Paily (VLSID, 2025)

A Wide Dynamic Range Differential Drive CMOS Rectifier for μWatts RF Energy Harvesting Systems. - Chaya Hegde; Arun Mohan 001; Saroj Mondal; Roy P. Paily (VLSID, 2025)

RAESC: A Reconfigurable AES Countermeasure Architecture for RISC-V With Enhanced Power Side-Channel Resilience. - Nayana Rajeev; Cathrene Biju; Titu Mary Ignatius; Roy Paily Palathinkal; Rekha K. James (IEEE Comput. Archit. Lett., 2025)

Boosting AES Intrinsic Resilience Using Split SubBytes Round Function Against Power Attacks. - Vishnu Padmakumar; Titu Mary Ignatius; Thockchom Birjit Singha; Roy Paily Palathinkal; Shaik Rafi Ahamed (IEEE Embed. Syst. Lett., 2025)

Design and Analysis of Energy Efficient Approximate Multipliers for Image Processing and Deep Neural Network. - Anupam Kumari; Roy Paily Palathinkal (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)