Quasi-two-dimensional subthreshold current model of deep submicrometer SOI drive-in gate controlled hybrid transistors with lateral non-uniform doping profile. - Ru Huang 001; Weihai Bu; Xing Zhang 002; Yangyuan Wang (Sci. China Ser. F Inf. Sci., 2001)

Extraction of the lateral distribution of interface traps in MOSFETs by a novel combined gated-diode technique. - Jin He 003; Xing Zhang 002; Ru Huang 001; Yangyuan Wang (Microelectron. Reliab., 2001)

Application of forward gated-diode R-G current method in extracting F-N stress-induced interface traps in SOI NMOSFETs. - Jin He 003; Xing Zhang 002; Ru Huang 001; Yangyuan Wang (Microelectron. Reliab., 2002)

Hot carrier degradation behavior in SOI dynamic-threshold-voltage nMOSFET's (n-DTMOSFET) measured by gated-diode configuration. - Ru Huang 001; Jinyan Wang; Jin He 003; Min Yu; Xing Zhang 002; Yangyuan Wang (Microelectron. Reliab., 2003)

Novel vertical channel double gate structures for high density and low power flash memory applications. - Ru Huang 001; FaLong Zhou; Yimao Cai; DaKe Wu; Xing Zhang 002 (Sci. China Ser. F Inf. Sci., 2008)

Novel devices and process for 32 nm CMOS technology and beyond. - Yangyuan Wang; Xing Zhang 002; Xiaoyan Liu; Ru Huang 001 (Sci. China Ser. F Inf. Sci., 2008)

A single-chip CMOS UHF RFID Reader transceiver for mobile applications. - Le Ye; Huailin Liao; Fei Song; Jiang Chen; Congyin Shi; Chen Li 014; Junhua Liu; Ru Huang 001; Jinshu Zhao; Huiling Xiao; Ruiqiang Liu; Xinan Wang (ESSCIRC, 2009)

Challenges of 22 nm and beyond CMOS technology. - Ru Huang 001; HanMing Wu; Jinfeng Kang; Deyuan Xiao; XueLong Shi; Xia An; Yu Tian; Runsheng Wang; Liangliang Zhang; Xing Zhang 002; Yangyuan Wang (Sci. China Ser. F Inf. Sci., 2009)

A Single-Chip CMOS UHF RFID Reader Transceiver for Chinese Mobile Applications. - Le Ye; Huailin Liao; Fei Song; Jiang Chen; Chen Li 014; Jinshu Zhao; Ruiqiang Liu; Chuan Wang; Congyin Shi; Junhua Liu; Ru Huang 001; Yangyuan Wang (IEEE J. Solid State Circuits, 2010)

Deteriorated radiation effects impact on the characteristics of MOS transistors with multi-finger configuration. - Jian Wang; Wenhua Wang; Ru Huang 001; Yunpeng Pei; Shoubin Xue; Xin'an Wang; Chunhui Fan; Yangyuan Wang (Microelectron. Reliab., 2010)

Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling. - Ru Huang 001; Runsheng Wang; Jing Zhuge; Changze Liu; Tao Yu; Liangliang Zhang; Xin Huang; Yujie Ai; Jinbin Zou; Yuchao Liu; Jiewen Fan; Huailin Liao; et al. (CICC, 2011)

An ultra-low power 400MHz OOK transceiver for medical implanted applications. - Junhua Liu; Chen Li 014; Long Chen 009; Yehui Xiao; Jiayi Wang; Huailin Liao; Ru Huang 001 (ESSCIRC, 2011)

A 0.47mW 6th-order 20MHz active filter using highly power-efficient Opamp. - Le Ye; Congyin Shi; Huailin Liao; Ru Huang 001 (ISCAS, 2011)

Resistance switching for RRAM applications. - Frederick T. Chen; Heng-Yuan Lee; Yu-Sheng Chen; Yenya Hsu; Lijie Zhang; Pang-Shiu Chen; Weisu Chen; Peiyi Gu; Wenhsing Liu; Sumin Wang; Chen-Han Tsai; Shyh-Shyuan Sheu; et al. (Sci. China Inf. Sci., 2011)

Editor's note. - Ru Huang 001; Bin Zhao; Runsheng Wang; Yimao Cai (Sci. China Inf. Sci., 2011)

HCI and NBTI induced degradation in gate-all-around silicon nanowire transistors. - Ru Huang 001; Runsheng Wang; Changze Liu; Liangliang Zhang; Jing Zhuge; Yu Tao; Jinbin Zou; Yuchao Liu; Yangyuan Wang (Microelectron. Reliab., 2011)

A +21.2 dBm out-of-band IIP3 0.2-3GHz RF front-end using impedance translation technique. - Long Chen 009; Chuan Wang; Chen Li 014; Le Ye; Huailin Liao; Ru Huang 001 (ISCAS, 2012)

Cost-efficient CMOS RF tunable bandpass filter with active inductor-less biquads. - Yixiao Wang; Le Ye; Huailin Liao; Ru Huang 001 (ISCAS, 2012)

Widely reconfigurable 8th-order chebyshev analog baseband IC with proposed push-pull op-amp for Software-Defined Radio in 65nm CMOS. - Le Ye; Yixiao Wang; Long Chen 009; Huailin Liao; Ru Huang 001 (ISCAS, 2012)

Self-heating effects in gate-all-around silicon nanowire MOSFETs: Modeling and analysis. - Xin Huang; Tianwei Zhang 002; Runsheng Wang; Changze Liu; Yuchao Liu; Ru Huang 001 (ISQED, 2012)

Theory and verification of operator design methodology. - Ziyi Hu; Yong Zhao 010; Xin'an Wang; Ru Huang 001; Teng Wang; Xing Zhang 002 (Sci. China Inf. Sci., 2012)

A novel compact low-power direct conversion receiver for mobile UHF RFID reader. - Shan Liu; Xin'an Wang; Jinpeng Shen; Bo Wang 016; Tao Ye; Ru Huang 001 (Sci. China Inf. Sci., 2012)

SAW-less GNSS front-end amplifier with 80.4-dB GSM blocker suppression using CMOS directional coupler notch filter. - Yongan Zheng; Le Ye; Long Chen 009; Huailin Liao; Ru Huang 001 (ISCAS, 2013)

Heterogeneous integration of nano enabling devices for 3D ICs. - Li Wang 058; Rui Ma 003; Chen Zhang 017; Zongyu Dong; Xin Wang 031; Zitao Shi; Jian Liu 027; Lin Lin 011; Hui Zhao 014; Fei Lu 004; Qiang Fang; Chen Yang; et al. (ISLPED, 2013)

A 65 mW fully integrated UHF-band CMMB tuner in 65 nm CMOS process. - Junhua Liu; Chen Li 014; Long Chen 009; Congyin Shi; Xuankai Weng; Yixiao Wang; Jiayi Wang; Yu Liao; Le Ye; Huailin Liao; Ru Huang 001 (Sci. China Inf. Sci., 2013)

Impacts of short-channel effects on the random threshold voltage variation in nanoscale transistors. - Runsheng Wang; Tao Yu; Ru Huang 001; Yangyuan Wang (Sci. China Inf. Sci., 2013)

A comb-gate silicon tunneling field effect transistor with improved on-state current. - Zhan Zhan; Qianqian Huang; Ru Huang 001; Wenzhe Jiang; Yangyuan Wang (Sci. China Inf. Sci., 2013)

Highly Power-Efficient Active-RC Filters With Wide Bandwidth-Range Using Low-Gain Push-Pull Opamps. - Le Ye; Congyin Shi; Huailin Liao; Ru Huang 001; Yangyuan Wang (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Resistive switching in organic memory devices for flexible applications. - Ru Huang 001; Yimao Cai; Yefan Liu; Wenliang Bai; Yongbian Kuang; Yangyuan Wang (ISCAS, 2014)

A novel low-noise high-linearity CMOS transmitter for mobile UHF RFID reader. - Shan Liu; Xin'an Wang; Jinpeng Shen; Bo Wang 016; Tao Ye; Ru Huang 001 (Sci. China Inf. Sci., 2014)

Self-Aligned Double Patterning Friendly Configuration for Standard Cell Library Considering Placement. - Jhih-Rong Gao; Bei Yu 001; Ru Huang 001; David Z. Pan (CoRR, 2014)

Duty cycle shift under static/dynamic aging in 28nm HK-MG technology. - Ketul B. Sutaria; Pengpeng Ren; Abinash Mohanty; Xixiang Feng; Runsheng Wang; Ru Huang 001; Yu Cao 001 (IRPS, 2015)

Influence of selector-introduced compliance current on HfOx RRAM switching operation. - Yichen Fang; Yimao Cai; Zongwei Wang 001; Zhizhen Yu; Xue Yang; Ru Huang 001 (NVMTS, 2015)

An electronic synapse based on tantalum oxide material. - Xue Yang; Yimao Cai; Zhenxing Zhang; Muxi Yu; Ru Huang 001 (NVMTS, 2015)

Ge surface passivation by GeO2 fabricated by N2O plasma oxidation. - Meng Lin; Xia An; Ming Li; Quanxin Yun; Min Li; Zhiqiang Li; Pengqiang Liu; Xing Zhang 002; Ru Huang 001 (Sci. China Inf. Sci., 2015)

Analytical current model of tunneling field-effect transistor considering the impacts of both gate and drain voltages on tunneling. - Chao Wang; Chunlei Wu; Jiaxin Wang; Qianqian Huang; Ru Huang 001 (Sci. China Inf. Sci., 2015)

Highly Reconfigurable Analog Baseband for Multistandard Wireless Receivers in 65-nm CMOS. - Yixiao Wang; Le Ye; Huailin Liao; Ru Huang 001; Yangyuan Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A 3D multi-layer CMOS-RRAM accelerator for neural network. - Hantao Huang; Leibin Ni; Yuhao Wang 002; Hao Yu 001; Zongwei Wang 001; Yimao Cai; Ru Huang 001 (3DIC, 2016)

Layout dependent BTI and HCI degradation in nano CMOS technology: A new time-dependent LDE and impacts on circuit at end of life. - Pengpeng Ren; Runsheng Wang; Ru Huang 001 (ICICDT, 2016)

Editor's note. - Ru Huang 001; Hiroshi Iwai; Cor Claeys; Simon Deleonibus; Runsheng Wang (Sci. China Inf. Sci., 2016)

Switching dynamics and computing applications of memristors: An overview. - Qingxi Duan; Teng Zhang; Minghui Yin; Caidie Cheng; Liying Xu; Yuchao Yang 001; Ru Huang 001 (ASICON, 2017)

A neural network circuit with associative learning and forgetting process based on memristor neuromorphic device. - Xiaoqiang Lv; Yimao Cai; Yuchao Yang 001; Zhizhen Yu; Yichen Fang; Zongwei Wang 001; Lindong Wu; Jianfeng Liu; Wanrong Zhang 002; Ru Huang 001 (ASICON, 2017)

How close to the CMOS voltage scaling limit for FinFET technology? - Near-threshold computing and stochastic computing. - Runsheng Wang; Xiaobo Jiang; Shaofeng Guo; Ru Huang 001 (ASICON, 2017)

A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement. - Xiaowei Han; Qian Jia; Hongbin Sun 001; Longfei Wang; Huaqiang Wu; Yimao Cai; Feng Zhang 014; Yongyi Xie; Fangxu Dong; Xiaoguang Wang 015; Xiaofei Xue; Li Pang; et al. (CICC, 2017)

Towards reliability-aware circuit design in nanoscale FinFET technology: - New-generation aging model and circuit reliability simulator. - Shaofeng Guo; Runsheng Wang; Zhuoqing Yu; Peng Hao; Pengpeng Ren; Yangyuan Wang; Siyu Liao; Chunyi Huang; Tianlei Guo; Alvin Chen; Jushan Xie; Ru Huang 001 (ICCAD, 2017)

Benchmarking TFET from a circuit level perspective: Applications and guideline. - Lingyi Guo; Le Ye; Cheng Chen; Qianqian Huang; Libo Yang; Zhu Lv; Xia An; Ru Huang 001 (ISCAS, 2017)

Compact digital-controlled neuromorphic circuit with low power consumption. - Jin Zhang; Yuan Wang 001; Xing Zhang 002; Ru Huang 001 (ISCAS, 2017)

Layout-dependent aging mitigation for critical path timing. - Che-Lun Hsu; Shaofeng Guo; Yibo Lin; Xiaoqing Xu; Meng Li 004; Runsheng Wang; Ru Huang 001; David Z. Pan (ASP-DAC, 2018)

A Compact and Accelerated Spike-based Neuromorphic VLSI Chip for Pattern Recognition. - Cheng Li; Yuan Wang 001; Jin Zhang; Xiaoxin Cui; Ru Huang 001 (BioCAS, 2018)

Compact modeling and simulation of accelerated circuit aging. - Devyani Patra; Jiayang Zhang; Runsheng Wang; Mehdi Katoozi; Ethan H. Cannon; Ru Huang 001; Yu Cao 001 (CICC, 2018)

Investigation on the amplitude coupling effect of random telegraph noise (RTN) in nanoscale FinFETs. - Shaofeng Guo; Zhenghan Lin; Runsheng Wang; Zexuan Zhang; Zhe Zhang 006; Yangyuan Wang; Ru Huang 001 (IRPS, 2018)

New insights into the HCI degradation of pass-gate transistor in advanced FinFET technology. - Pengpeng Ren; Changze Liu; Sanping Wan; Jiayang Zhang; Zhuoqing Yu; Nie Liu; Yongsheng Sun; Runsheng Wang; Canhui Zhan; Zhenghao Gan; Waisum Wong; Yu Xia; et al. (IRPS, 2018)

Evaluation of SRAM Vmin shift induced by random telegraph noise (RTN): physical understanding and prediction method. - Shaofeng Guo; Zhenghan Lin; Runsheng Wang; Dongyuan Mao; Yangyuan Wang; Ru Huang 001 (ISCAS, 2018)

Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity. - Guangyi Lu; Yuan Wang 001; Lizhong Zhang; Yize Wang; Ru Huang 001; Xing Zhang 002 (ISCAS, 2018)

Combinational Access Tunnel FET SRAM for Ultra-Low Power Applications. - Libo Yang; Jiadi Zhu; Cheng Chen; Zhixuan Wang; Zexue Liu; Qianqian Huang; Le Ye; Ru Huang 001 (ISCAS, 2018)

A Multi-Mode Silicon Neuron Circuit With High Robustness Against PVT Variation. - Lu Zhang; Jin Zhang; Yuan Wang 001; Xing Zhang 002; Ru Huang 001 (ISCAS, 2018)

Enhancement of HfO2 Based RRAM Performance Through Hexagonal Boron Nitride Interface Layer. - Yi-Shao Chen; Zongwei Wang 001; Zhihong Zhang; Li Wang 058; Yichen Fang; Jen-Chung Lou; Kaihui Liu; Jintong Xu; Yimao Cai; Ru Huang 001 (NVMTS, 2018)

Margin Dependence on Array Size for Asymmetric Resistive Memory Cell. - Zhizhen Yu; Yichen Fang; Zongwei Wang 001; Yimao Cai; Ru Huang 001; Jintong Xu (NVMTS, 2018)

Integration of biocompatible organic resistive memory and photoresistor for wearable image sensing application. - Qingyu Chen; Min Lin; Yichen Fang; Zongwei Wang 001; Yuchao Yang 001; Jintong Xu; Yimao Cai; Ru Huang 001 (Sci. China Inf. Sci., 2018)

GeC film with high substitutional carbon concentration formed by ion implantation and solid phase epitaxy for strained Ge n-MOSFETs. - Bingxin Zhang; Xia An; Xiangyang Hu; Ming Li; Xing Zhang 002; Ru Huang 001 (Sci. China Inf. Sci., 2018)

Improvement of thermal stability of nickel germanide using nitrogen plasma pretreatment for germanium-based technology. - Bingxin Zhang; Xia An; Pengqiang Liu; Xiangyang Hu; Ming Li; Xing Zhang 002; Ru Huang 001 (Sci. China Inf. Sci., 2018)

Investigation on NBTI-induced dynamic variability in nanoscale CMOS devices: Modeling, experimental evidence, and impact on circuits. - Shaofeng Guo; Runsheng Wang; Pengpeng Ren; Changze Liu; Mulong Luo; Xiaobo Jiang; Yangyuan Wang; Ru Huang 001 (Microelectron. Reliab., 2018)

Neuromorphic Devices and Networks Based on Memristors with Ionic Dynamics. - Yuchao Yang 001; Ke Yang; Ru Huang 001 (Handbook of Memristor Networks, 2019)

Realization of Nanoscale Neuromorphic Memristor Array with Low Power Consumption. - Caidie Cheng; Teng Zhang; Chang Liu; Jiadi Zhu; Liying Xu; Xiaoqin Yan; Yuchao Yang 001; Ru Huang 001 (ASICON, 2019)

OMI/TMI-based Modeling and Fast Simulation of Random Telegraph Noise (RTN) in Advanced Logic Devices and Circuits. - Runsheng Wang; Zhe Zhang 006; Shaofeng Guo; Qingxue Wang; Dehuang Wu; Joddy Wang; Ru Huang 001 (ASICON, 2019)

An Energy-Efficient Mixed-Signal Parallel Multiply-Accumulate (MAC) Engine Based on Stochastic Computing. - Xinyue Zhang 002; Jiahao Song; Yuan Wang 001; Yawen Zhang; Zuodong Zhang; Runsheng Wang; Ru Huang 001 (ASICON, 2019)

An Energy-Efficient Computing-in-Memory Neuromorphic System with On-Chip Training. - Zhao Zhao; Yuan Wang 001; Xinyue Zhang 002; Xiaoxin Cui; Ru Huang 001 (BioCAS, 2019)

Memory System Designed for Multiply-Accumulate (MAC) Engine Based on Stochastic Computing. - Xinyue Zhang 002; Yuan Wang 001; Yawen Zhang; Jiahao Song; Zuodong Zhang; Kaili Cheng; Runsheng Wang; Ru Huang 001 (ICICDT, 2019)

A Sparse Event-Driven Unsupervised Learning Network with Adaptive Exponential Integrate-and-Fire Model. - Zhao Zhao; Yuan Wang 001; Cheng Li; Xiaoxin Cui; Ru Huang 001 (ICICDT, 2019)

Ultra-Low Power Hybrid TFET-MOSFET Topologies for Standard Logic Cells with Improved Comprehensive Performance. - Zhixuan Wang; Yuan Zhong; Cheng Chen; Le Ye; Qianqian Huang; Libo Yang; Yangyuan Wang; Ru Huang 001 (ISCAS, 2019)

Enhance the Robustness to Time Dependent Variability of ReRAM-Based Neuromorphic Computing Systems with Regularization and 2R Synapse. - Qilin Zheng; Jian Kang; Zongwei Wang 001; Yimao Cai; Ru Huang 001; Bing Li 017; Yiran Chen 001; Hai Helen Li (ISCAS, 2019)

A Survey of Computation-Driven Data Encoding. - Weikang Qian; Runsheng Wang; Yuan Wang 001; Marc D. Riedel; Ru Huang 001 (SiPS, 2019)

Parallel Convolutional Neural Network (CNN) Accelerators Based on Stochastic Computing. - Yawen Zhang; Xinyue Zhang 002; Jiahao Song; Yuan Wang 001; Ru Huang 001; Runsheng Wang (SiPS, 2019)

Investigation of NbOx-based volatile switching device with self-rectifying characteristics. - Yichen Fang; Zongwei Wang 001; Caidie Cheng; Zhizhen Yu; Teng Zhang; Yuchao Yang 001; Yimao Cai; Ru Huang 001 (Sci. China Inf. Sci., 2019)

Low power and high uniformity of HfO x -based RRAM via tip-enhanced electric fields. - Xiaokang Li; Baotong Zhang; Bowen Wang; Xiaoyan Xu; Yuancheng Yang; Shuang Sun; Qifeng Cai; Shijie Hu; Xia An; Ming Li; Ru Huang 001 (Sci. China Inf. Sci., 2019)

Deep insight into the voltage amplification effect from ferroelectric negative capacitance. - Huimin Wang; Qianqian Huang; Mengxuan Yang; Xing Zhang 002; Ru Huang 001 (Sci. China Inf. Sci., 2019)

A Parallel Bitstream Generator for Stochastic Computing. - Yawen Zhang; Runsheng Wang; Xinyue Zhang 002; Zherui Zhang; Jiahao Song; Zuodong Zhang; Yuan Wang 001; Ru Huang 001 (CoRR, 2019)

New-Generation Design-Technology Co-Optimization (DTCO): Machine-Learning Assisted Modeling Framework. - Zhe Zhang 006; Runsheng Wang; Cheng Chen; Qianqian Huang; Yangyuan Wang; Cheng Hu; Dehuang Wu; Joddy Wang; Ru Huang 001 (CoRR, 2019)

Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks. - Qilin Zheng; Zongwei Wang 001; Zishun Feng; Bonan Yan; Yimao Cai; Ru Huang 001; Yiran Chen 001; Chia-Lin Yang; Hai Helen Li (DAC, 2020)

When Sorting Network Meets Parallel Bitstreams: A Fault-Tolerant Parallel Ternary Neural Network Accelerator based on Stochastic Computing. - Yawen Zhang; Sheng Lin 001; Runsheng Wang; Yanzhi Wang; Yuan Wang 001; Weikang Qian; Ru Huang 001 (DATE, 2020)

Reliability-Enhanced Circuit Design Flow Based on Approximate Logic Synthesis. - Zuodong Zhang; Runsheng Wang; Zhe Zhang 006; Ru Huang 001; Chang Meng; Weikang Qian; Zhuangzhuang Zhou (ACM Great Lakes Symposium on VLSI, 2020)

MobiLattice: A Depth-wise DCNN Accelerator with Hybrid Digital/Analog Nonvolatile Processing-In-Memory Block. - Qilin Zheng; Xingchen Li; Zongwei Wang 001; Guangyu Sun 003; Yimao Cai; Ru Huang 001; Yiran Chen 001; Hai Li 001 (ICCAD, 2020)

A 1μW-to-158μW Output Power Pseudo Open-Loop Boost DC-DC with 86.7% Peak Efficiency using Frequency-Programmable Oscillator and Hybrid Zero Current Detection. - Xiaolong Chen; Enbin Gong; Hao Zhang 119; Le Ye; Ru Huang 001 (ISCAS, 2020)

2.4-GHz 16-QAM Passive Backscatter Transmitter for Wireless Self-Power Chips in IoT. - Enbin Gong; Hao Zhang 119; Xiaolong Chen; Le Ye; Ru Huang 001 (ISCAS, 2020)

Accurate and Energy-Efficient Implementation of Non-Linear Adder in Parallel Stochastic Computing using Sorting Network. - Yawen Zhang; Runsheng Wang; Yixuan Hu; Weikang Qian; Yanzhi Wang; Yuan Wang 001; Ru Huang 001 (ISCAS, 2020)

20.2 A 57nW Software-Defined Always-On Wake-Up Chip for IoT Devices with Asynchronous Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC. - Zhixuan Wang; Le Ye; Hao Zhanq; Jiayoon Ru; Haitao Fan; Yangyuan Wang; Ru Huang 001 (ISSCC, 2020)

Rotational Pattern Recognition by Spiking Correlated Neural Network Based on Dual-Gated MoS 2 Neuristor. - Lin Bao; Zongwei Wang 001; Zhizhen Yu; Yaotian Ling; Yimao Cai; Ru Huang 001 (Adv. Intell. Syst., 2020)

Memristor-Based Biologically Plausible Memory Based on Discrete and Continuous Attractor Networks for Neuromorphic Systems. - Yanghao Wang; Liutao Yu; Si Wu; Ru Huang 001; Yuchao Yang 001 (Adv. Intell. Syst., 2020)

A photomemory by selective-assembling hybrid porphyrin-silicon nanowire field-effect transistor. - Gong Chen; Bocheng Yu; Xiaokang Li; Xiaoqiao Dong; Xiaoyan Xu; Zhihong Li; Ru Huang 001; Ming Li (Sci. China Inf. Sci., 2020)

Complementary tunneling transistors based on WSe2/SnS2 van der Waals heterostructure. - Rundong Jia; Liang Chen; Qianqian Huang; Ru Huang 001 (Sci. China Inf. Sci., 2020)

Vertical SnS2/Si heterostructure for tunnel diodes. - Rundong Jia; Qianqian Huang; Ru Huang 001 (Sci. China Inf. Sci., 2020)

High-quality and large-grain epi-like Si film by NiSi2-seed initiated lateral epitaxial crystallization (SILEC). - Yuancheng Yang; Baotong Zhang; Xiaoqiao Dong; Xiaokang Li; Shuang Sun; Qifeng Cai; Ran Bi; Xiaoyan Xu; Ming Li; Ru Huang 001 (Sci. China Inf. Sci., 2020)

Efficient 16 Boolean logic and arithmetic based on bipolar oxide memristors. - Rui Yuan; Mingyuan Ma; Liying Xu; Zhenhua Zhu; Qingxi Duan; Teng Zhang; Yu Zhu; Yu Wang 002; Ru Huang 001; Yuchao Yang 001 (Sci. China Inf. Sci., 2020)

DaSGD: Squeezing SGD Parallelization Performance in Distributed Training Using Delayed Averaging. - Qinggang Zhou; Yawen Zhang; Pengcheng Li; Xiaoyong Liu; Jun Yang; Runsheng Wang; Ru Huang 001 (CoRR, 2020)

Parallel Hybrid Stochastic-Binary-Based Neural Network Accelerators. - Yawen Zhang; Runsheng Wang; Xinyue Zhang 002; Yuan Wang 001; Ru Huang 001 (IEEE Trans. Circuits Syst., 2020)

Circuit Reliability Comparison Between Stochastic Computing and Binary Computing. - Zuodong Zhang; Runsheng Wang; Zhe Zhang 006; Yawen Zhang; Shaofeng Guo; Ru Huang 001 (IEEE Trans. Circuits Syst., 2020)

A 16Kb Transpose 6T SRAM In-Memory-Computing Macro based on Robust Charge-Domain Computing. - Jiahao Song; Yuan Wang 001; Xiyuan Tang; Runsheng Wang; Ru Huang 001 (A-SSCC, 2021)

SWIFT: Small-World-based Structural Pruning to Accelerate DNN Inference on FPGA. - Yufei Ma 002; Gokul Krishnan; Yu Cao 001; Le Ye; Ru Huang 001 (FPGA, 2021)

DALTA: A Decomposition-based Approximate Lookup Table Architecture. - Chang Meng; Zhiyuan Xiang; Niyiqiu Liu; Yixuan Hu; Jiahao Song; Runsheng Wang; Ru Huang 001; Weikang Qian (ICCAD, 2021)

Can Emerging Computing Paradigms Help Enhancing Reliability Towards the End of Technology Roadmap? - Runsheng Wang; Zuodong Zhang; Yawen Zhang; Yixuan Hu; Yanan Sun 003; Weikang Qian; Ru Huang 001 (IRPS, 2021)

A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations. - Yisong Kuang; Xiaoxin Cui; Yi Zhong; Kefei Liu 002; Chenglong Zou; Zhenhui Dai; Dunshan Yu; Yuan Wang 001; Ru Huang 001 (ISCAS, 2021)

Approximate Logic Synthesis in the Loop for Designing Low-Power Neural Network Accelerator. - Yifan Qian; Chang Meng; Yawen Zhang; Weikang Qian; Runsheng Wang; Ru Huang 001 (ISCAS, 2021)

A High Accuracy Multiple-Command Speech Recognition ASIC Based on Configurable One-Dimension Convolutional Neural Network. - Lindong Wu; Zongwei Wang 001; Ming Zhao; Wei Hu; Yimao Cai; Ru Huang 001 (ISCAS, 2021)

A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS. - Yi Zhong; Xiaoxin Cui; Yisong Kuang; Kefei Liu 002; Yuan Wang 001; Ru Huang 001 (ISCAS, 2021)

Session 16 Overview: Computation in Memory Memory Subcommittee. - Meng-Fan Chang; Ru Huang 001; Seung-Jun Bae (ISSCC, 2021)

5.1 A 1.5μW 0.135pJ·%RH2 CMOS Humidity Sensor Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array. - Heyi Li; Zhichao Tan; Yuanxin Bao; Han Xiao 006; Hao Zhang 119; Kaixuan Du; Yihan Zhang 002; Le Ye; Ru Huang 001 (ISSCC, 2021)

12.1 A 148nW General-Purpose Event-Driven Intelligent Wake-Up Chip for AIoT Devices Using Asynchronous Spike-Based Feature Extractor and Convolutional Neural Network. - Zhixuan Wang; Le Ye; Ying Liu 069; Peng Zhou; Zhichao Tan; Haitao Fan; Yihan Zhang 002; Jiayoon Ru; Yangyuan Wang; Ru Huang 001 (ISSCC, 2021)

In-memory computing with emerging nonvolatile memory devices. - Caidie Cheng; Pek Jun Tiw; Yimao Cai; Xiaoqin Yan; Yuchao Yang 001; Ru Huang 001 (Sci. China Inf. Sci., 2021)

Layout dependence of total-ionizing-dose response in 65-nm bulk Si pMOSFET. - Zhexuan Ren; Xia An; Gensong Li; Xing Zhang 002; Ru Huang 001 (Sci. China Inf. Sci., 2021)

Energy-Efficient CMOS Humidity Sensors Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array. - Heyi Li; Zhichao Tan; Yuanxin Bao; Han Xiao 006; Hao Zhang 119; Kaixuan Du; Linxiao Shen; Jiayoon Ru; Yihan Zhang 002; Le Ye; Ru Huang 001 (IEEE J. Solid State Circuits, 2021)

A 148-nW Reconfigurable Event-Driven Intelligent Wake-Up System for AIoT Nodes Using an Asynchronous Pulse-Based Feature Extractor and a Convolutional Neural Network. - Zhixuan Wang; Ying Liu 069; Peng Zhou; Zhichao Tan; Haitao Fan; Yihan Zhang 002; Linxiao Shen; Jiayoon Ru; Yangyuan Wang; Le Ye; Ru Huang 001 (IEEE J. Solid State Circuits, 2021)

A Software-Defined Always-On System With 57-75-nW Wake-Up Function Using Asynchronous Clock-Free Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC. - Zhixuan Wang; Hao Zhang 119; Yihan Zhang 002; Linxiao Shen; Jiayoon Ru; Haitao Fan; Zhichao Tan; Yangyuan Wang; Le Ye; Ru Huang 001 (IEEE J. Solid State Circuits, 2021)

TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks. - Jiahao Song; Yuan Wang 001; Minguang Guo; Xiang Ji; Kaili Cheng; Yixuan Hu; Xiyuan Tang; Runsheng Wang; Ru Huang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Optimization Schemes for In-Memory Linear Regression Circuit With Memristor Arrays. - Shiqing Wang; Zhong Sun; Yuheng Liu; Shengyu Bao; Yimao Cai; Daniele Ielmini; Ru Huang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process. - Zhixuan Wang; Le Ye; Qianqian Huang; Kaixuan Du; Zhichao Tan; Yangyuan Wang; Ru Huang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Re-Assessment of Steep-Slope Device Design From a Circuit-Level Perspective Using Novel Evaluation Criteria and Model-Less Method. - Zhixuan Wang; Le Ye; Qianqian Huang; Yangyuan Wang; Ru Huang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

The Challenges and Emerging Technologies for Low-Power Artificial Intelligence IoT Systems. - Le Ye; Zhixuan Wang; Ying Liu 069; Peiyu Chen; Heyi Li; Hao Zhang 119; Meng Wu 005; Wei He; Linxiao Shen; Yihan Zhang 002; Zhichao Tan; Yangyuan Wang; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS. - Yisong Kuang; Xiaoxin Cui; Yi Zhong; Kefei Liu 002; Chenglong Zou; Zhenhui Dai; Yuan Wang 001; Dunshan Yu; Ru Huang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Time Complexity of In-Memory Matrix-Vector Multiplication. - Zhong Sun; Ru Huang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Mapping Model of SNNs to Neuromorphic Hardware. - Xiuping Cui; Xiaochen Hao; Yun Liang 001; Guangyu Sun 003; Xiaoxin Cui; Yuan Wang 001; Ru Huang 001 (AICAS, 2022)

Heterogeneous Memory Architecture Accommodating Processing-in-Memory on SoC for AIoT Applications. - Kangyi Qiu; Yaojun Zhang; Bonan Yan; Ru Huang 001 (ASP-DAC, 2022)

A 77μW 115dB-Dynamic-Range 586fA-Sensitivity Current-Domain Continuous-Time Zoom ADC with Pulse-Width-Modulated Resistor DAC and Background Offset Compensation Scheme. - Hao Zhang 119; Linxiao Shen; Shichuang Zhang; Heyi Li; Yihan Zhang 002; Zhichao Tan; Ru Huang 001; Le Ye (CICC, 2022)

ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapses. - Ziru Li; Qilin Zheng; Bonan Yan; Ru Huang 001; Bing Li 005; Yiran Chen 001 (DAC, 2022)

AVATAR: an aging- and variation-aware dynamic timing analyzer for application-based DVAFS. - Zuodong Zhang; Zizheng Guo; Yibo Lin; Runsheng Wang; Ru Huang 001 (DAC, 2022)

EventTimer: Fast and Accurate Event-Based Dynamic Timing Analysis. - Zuodong Zhang; Zizheng Guo; Yibo Lin; Runsheng Wang; Ru Huang 001 (DATE, 2022)

Compact Modeling of Phase Change Memory with Parameter Extractions. - Feilong Ding; Xi Li; Yihan Chen; Zhitang Song; Runsheng Wang; Clarissa C. Prawoto; Mansun Chan; Lining Zhang; Ru Huang 001 (ESSDERC, 2022)

Enabling High-Quality Uncertainty Quantification in a PIM Designed for Bayesian Neural Network. - Xingchen Li; Bingzhe Wu; Guangyu Sun 003; Zhe Zhang 006; Zhihang Yuan; Runsheng Wang; Ru Huang 001; Dimin Niu; Hongzhong Zheng; Zhichao Lu; Liang Zhao; Meng-Fan Marvin Chang; et al. (HPCA, 2022)

DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional Networks. - Yikan Qiu; Yufei Ma 002; Wentao Zhao; Meng Wu 005; Le Ye; Ru Huang 001 (ICCAD, 2022)

DeePEB: A Neural Partial Differential Equation Solver for Post Exposure Baking Simulation in Lithography. - Qipan Wang; Xiaohan Gao; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICCAD, 2022)

New Insight into the Aging Induced Retention Time Degraded of Advanced DRAM Technology. - Yong Liu; Pengpeng Ren; Da Wang; Longda Zhou; Zhigang Ji; Junhua Liu; Runsheng Wang; Ru Huang 001 (IRPS, 2022)

Towards the Characterization of Full ID-VG Degradation in Transistors for Future Analog Applications. - Pengpeng Ren; Xinfa Zhang; Junhua Liu; Runsheng Wang; Zhigang Ji; Ru Huang 001 (IRPS, 2022)

Characterization and Modelling of Hot Carrier Degradation in pFETs under Vd>Vg Condition for sub-20nm DRAM Technologies. - Da Wang; Yong Liu; Pengpeng Ren; Longda Zhou; Zhigang Ji; Junhua Liu; Runsheng Wang; Ru Huang 001 (IRPS, 2022)

An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique. - Ying Liu 069; Zhixuan Wang; Wei He; Linxiao Shen; Yihan Zhang 002; Peiyu Chen; Meng Wu 005; Hao Zhang 119; Peng Zhou; Jinguang Liu; Guangyu Sun 003; Jiayoon Ru; et al. (ISSCC, 2022)

A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications. - Bonan Yan; Jeng-Long Hsu; Pang-Cheng Yu; Chia-Chi Lee; Yaojun Zhang; Wenshuo Yue; Guoqiang Mei; Yuchao Yang 001; Yue Yang; Hai Li 001; Yiran Chen 001; Ru Huang 001 (ISSCC, 2022)

Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms. - Yihan Zhang 002; Chang Xue; Xiao Wang; Tianyi Liu; Jihang Gao; Peiyu Chen; Jinguang Liu; Linan Sun; Linxiao Shen; Jiayoon Ru; Le Ye; Ru Huang 001 (ISSCC, 2022)

A Novel Ambipolar Ferroelectric Tunnel FinFET based Content Addressable Memory with Ultra-low Hardware Cost and High Energy Efficiency for Machine Learning. - Jin Luo; Weikai Xu; Boyi Fu; Zheru Yu; Mengxuan Yang; Yiqing Li; Qianqian Huang; Ru Huang 001 (VLSI Technology and Circuits, 2022)

Artificial Multisensory Neurons with Fused Haptic and Temperature Perception for Multimodal In-Sensor Computing. - Qingxi Duan; Teng Zhang; Chang Liu; Rui Yuan; Ge Li; Pek Jun Tiw; Ke Yang; Chen Ge; Yuchao Yang 001; Ru Huang 001 (Adv. Intell. Syst., 2022)

In Materia Neuron Spiking Plasticity for Sequential Event Processing Based on Dual-Mode Memristor. - Linbo Shan; Zongwei Wang 001; Lin Bao; Shengyu Bao; Yabo Qin; Yaotian Ling; Guandong Bai; John Robertson; Yimao Cai; Ru Huang 001 (Adv. Intell. Syst., 2022)

CircuitNet: an open-source dataset for machine learning applications in electronic design automation (EDA). - Zhuomin Chai; Yuxiang Zhao; Yibo Lin; Wei Liu 160; Runsheng Wang; Ru Huang 001 (Sci. China Inf. Sci., 2022)

Single event transients induced by pulse laser in Ge pMOSFETs and its supply voltage dependence. - Jingyi Liu; Xia An; Gensong Li; Zhexuan Ren; Ming Li; Xing Zhang 002; Ru Huang 001 (Sci. China Inf. Sci., 2022)

Experimental investigation of the gate voltage range of negative differential capacitance in ferroelectric transistors. - Mengxuan Yang; Qianqian Huang; Chang Su; Liang Chen; Yangyuan Wang; Ru Huang 001 (Sci. China Inf. Sci., 2022)

Physical investigation of subthreshold swing degradation behavior in negative capacitance FET. - Mengxuan Yang; Qianqian Huang; Kaifeng Wang; Chang Su; Liang Chen; Yangyuan Wang; Ru Huang 001 (Sci. China Inf. Sci., 2022)

MPCViT: Searching for MPC-friendly Vision Transformer with Heterogeneous Attention. - Wenxuan Zeng; Meng Li 004; Wenjie Xiong 001; Wenjie Lu; Jin Tan; Runsheng Wang; Ru Huang 001 (CoRR, 2022)

Memristive devices based hardware for unlabeled data processing. - Zhuojian Xiao; Bonan Yan; Teng Zhang; Ru Huang 001; Yuchao Yang 001 (Neuromorph. Comput. Eng., 2022)

PIMulator-NN: An Event-Driven, Cross-Level Simulation Framework for Processing-In-Memory-Based Neural Network Accelerators. - Qilin Zheng; Xingchen Li; Yijin Guan; Zongwei Wang 001; Yimao Cai; Yiran Chen 001; Guangyu Sun 003; Ru Huang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

VSDCA: A Voltage Sensing Differential Column Architecture Based on 1T2R RRAM Array for Computing-in-Memory Accelerators. - Zhaokun Jing; Bonan Yan; Yuchao Yang 001; Ru Huang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Modeling and Mitigating the Interconnect Resistance Issue in Analog RRAM Matrix Computing Circuits. - Yubiao Luo; Shiqing Wang; Pushen Zuo; Zhong Sun; Ru Huang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator. - Yisong Kuang; Xiaoxin Cui; Zilin Wang; Chenglong Zou; Yi Zhong; Kefei Liu 002; Zhenhui Dai; Dunshan Yu; Yuan Wang 001; Ru Huang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Live Demonstration: SRAM Compute-In-Memory Based Visual & Aural Recognition System. - Anjunyi Fan; Bo Hu; Zhonghua Jin; Haiyue Han; Yaojun Zhang; Yue Yang; Yuchao Yang 001; Bonan Yan; Ru Huang 001 (AICAS, 2023)

Device-Architecture Co-optimization for RRAM-based In-memory Computing. - Yimao Cai; Yi Gao; Zongwei Wang 001; Lin Bao; Ling Liang; Qilin Zheng; Cuimei Wang; Ru Huang 001 (ASICON, 2023)

Not your father's stochastic computing (SC)! Efficient yet Accurate End-to-End SC Accelerator Design. - Meng Li 004; Yixuan Hu; Tengyu Zhang; Renjie Wei; Yawen Zhang; Ru Huang 001; Runsheng Wang (ASICON, 2023)

A Novel TFET-MOSFET Hybrid SRAM for Ultra-Low-Power Applications. - Renjie Wei; Kaifeng Wang; Zhixuan Wang; Libo Yang; Fangxing Zhang; Yongqin Wu; Ye Ren; Le Ye; Lining Zhang; Weihai Bu; Ru Huang 001; Qianqian Huang (ASICON, 2023)

RIMAC: An Array-Level ADC/DAC-Free ReRAM-Based in-Memory DNN Processor with Analog Cache and Computation. - Peiyu Chen; Meng Wu 005; Yufei Ma 002; Le Ye; Ru Huang 001 (ASP-DAC, 2023)

A A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology. - Ying Liu 069; Zhiyuan Chen 009; Zhixuan Wang; Wentao Zhao; Wei He; Jianfeng Zhu; Oijun Wang; Ning Zhang; Tianyu Jia; Yufei Ma 002; Le Ye; Ru Huang 001 (CICC, 2023)

A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC. - Jiahao Song; Xiyuan Tang; Haoyang Luo; Haoyi Zhang; Xin Qiao; Zixuan Sun; Xiangxing Yang; Yuan Wang 001; Runsheng Wang; Ru Huang 001 (CICC, 2023)

A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware. - Yanchi Dong; Tianyu Jia; Kaixuan Du; Yiqi Jing; Qijun Wang; Pixian Zhan; Yadong Zhang; Fengyun Yan; Yufei Ma 002; Yun Liang 001; Le Ye; Ru Huang 001 (DAC, 2023)

General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism. - Zizheng Guo; Zuodong Zhang; Xun Jiang 002; Wuxi Li; Yibo Lin; Runsheng Wang; Ru Huang 001 (DAC, 2023)

Efficient Non-Linear Adder for Stochastic Computing with Approximate Spatial-Temporal Sorting Network. - Yixuan Hu; Tengyu Zhang; Meng Li 004; Renjie Wei; Liangzhen Lai; Yuan Wang 001; Runsheng Wang; Ru Huang 001 (DAC, 2023)

MTL-Designer: An Integrated Flow for Analysis and Synthesis of Microstrip Transmission Line. - Qipan Wang; Ping Liu; Liguo Jiang; Mingjie Liu; Yibo Lin; Runsheng Wang; Ru Huang 001 (DAC, 2023)

Accurate yet Efficient Stochastic Computing Neural Acceleration with High Precision Residual Fusion. - Yixuan Hu; Tengyu Zhang; Renjie Wei; Meng Li 004; Runsheng Wang; Yuan Wang 001; Ru Huang 001 (DATE, 2023)

SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility. - Haoyi Zhang; Xiaohan Gao; Haoyang Luo; Jiahao Song; Xiyuan Tang; Junhua Liu; Yibo Lin; Runsheng Wang; Ru Huang 001 (DATE, 2023)

READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction. - Zuodong Zhang; Meng Li 004; Yibo Lin; Runsheng Wang; Ru Huang 001 (DATE, 2023)

A 12.5-ppm/°C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology. - Xinhang Xu; Linxiao Shen; Siyuan Ye; Jiayi Wu; Zhuoyi Chen; Jihang Gao; Jiajia Cui; Yihan Zhang 002; Ru Huang 001; Le Ye (ESSCIRC, 2023)

New Insights into Read Current Margin and Memory Window of HfO2-based Ferroelectric FET with Re-exploration of the Role of Ferroelectric Dynamics and Interface Charges during Readout. - Chang Su; Zhongxin Liang; Zhiyuan Fu; Shaodi Xu; Kaifeng Wang; Puyang Cai; Liang Chen; Ru Huang 001; Qianqian Huang (ESSDERC, 2023)

First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology. - Kaifeng Wang; Yongqin Wu; Ye Ren; Renjie Wei; Zerui Chen; Jianfeng Hang; Zhixuan Wang; Fangxing Zhang; Lining Zhang; Chunyu Peng; Xiulong Wu; Le Ye; et al. (ESSDERC, 2023)

Invited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms. - Xun Jiang 002; Zizheng Guo; Zhuomin Chai; Yuxiang Zhao; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICCAD, 2023)

Falcon: Accelerating Homomorphically Encrypted Convolutions for Efficient Private Mobile Network Inference. - Tianshi Xu; Meng Li 004; Runsheng Wang; Ru Huang 001 (ICCAD, 2023)

READ: Reliability-Enhanced Accelerator Dataflow Optimization Using Critical Input Pattern Reduction. - Zuodong Zhang; Renjie Wei; Meng Li 004; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICCAD, 2023)

Memory-aware Scheduling for Complex Wired Networks with Iterative Graph Optimization. - Shuzhang Zhong; Meng Li 004; Yun Liang 001; Runsheng Wang; Ru Huang 001 (ICCAD, 2023)

MPCViT: Searching for Accurate and Efficient MPC-Friendly Vision Transformer with Heterogeneous Attention. - Wenxuan Zeng; Meng Li 004; Wenjie Xiong 001; Tong Tong; Wen-Jie Lu; Jin Tan; Runsheng Wang; Ru Huang 001 (ICCV, 2023)

A High-Throughput and Configurable TRNG Based on Dual-Mode Memristor for Stochastic Computing. - Zezhi Cheng; Yabo Qin; Zongwei Wang 001; Feng Zou; Cuimei Wang; Yimao Cai; Ru Huang 001 (ICTA, 2023)

Design Considerations of Multi-Level 1S1R Cell for In-Memory Computing. - Jinshan Li; Zongwei Wang 001; Cuimei Wang; Yimao Cai; Ru Huang 001 (ICTA, 2023)

Investigation of Hot Carrier Enhanced Body Bias Effect in Advanced FinFET Technology. - Zixuan Sun; Haoran Lu; Yongkang Xue; Wenpu Luo; Zirui Wang; Jiayang Zhang; Zhigang Ji; Runsheng Wang; Ru Huang 001 (IRPS, 2023)

Double-sided Row Hammer Effect in Sub-20 nm DRAM: Physical Mechanism, Key Features and Mitigation. - Longda Zhou; Jie Li; Zheng Qiao; Pengpeng Ren; Zixuan Sun; Jianping Wang; Blacksmith Wu; Zhigang Ji; Runsheng Wang; Kanyu Cao; Ru Huang 001 (IRPS, 2023)

A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing. - Peiyu Chen; Meng Wu 005; Wentao Zhao; Jiajia Cui; Zhixuan Wang; Yadong Zhang; Qijun Wang; Jiayoon Ru; Linxiao Shen; Tianyu Jia; Yufei Ma 002; Le Ye; et al. (ISSCC, 2023)

A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting. - Jihang Gao; Linxiao Shen; Heyi Li; Siyuan Ye; Jie Li; Xinhang Xu; Jiajia Cui; Yunhung Gao; Ru Huang 001; Le Ye (ISSCC, 2023)

A 0.954nW 32kHz Crystal Oscillator in 22nm CMOS with Gm-C-Based Current Injection Control. - Yihan Zhang 002; You You; Wenjie Ren; Xinhang Xu; Linxiao Shen; Jiayoon Ru; Ru Huang 001; Le Ye (ISSCC, 2023)

Khronos: Fusing Memory Access for Improved Hardware RTL Simulation. - Kexing Zhou; Yun Liang 001; Yibo Lin; Runsheng Wang; Ru Huang 001 (MICRO, 2023)

CoPriv: Network/Protocol Co-Optimization for Communication-Efficient Private Inference. - Wenxuan Zeng; Meng Li 004; Haichuan Yang; Wen-jie Lu; Runsheng Wang; Ru Huang 001 (NeurIPS, 2023)

Catching the Missing EM Consequence in Soft Breakdown Reliability in Advanced FinFETs: Impacts of Self-heating, On-State TDDB, and Layout Dependence. - Zuoyuan Dong; Zixuan Sun; Xin Yang; Xiaomei Li; Yongkang Xue; Chen Luo; Puyang Cai; Zirui Wang; Shuying Wang; Yewei Zhang; Chaolun Wang; Pengpeng Ren; et al. (VLSI Technology and Circuits, 2023)

EBSR: Enhanced Binary Neural Network for Image Super-Resolution. - Renjie Wei; Shuwen Zhang; Zechun Liu; Meng Li 004; Yuchen Fan; Runsheng Wang; Ru Huang 001 (CoRR, 2023)

HybridNet: Dual-Branch Fusion of Geometrical and Topological Views for VLSI Congestion Prediction. - Yuxiang Zhao; Zhuomin Chai; Yibo Lin; Runsheng Wang; Ru Huang 001 (CoRR, 2023)

CoPriv: Network/Protocol Co-Optimization for Communication-Efficient Private Inference. - Wenxuan Zeng; Meng Li 004; Haichuan Yang; Wenjie Lu; Runsheng Wang; Ru Huang 001 (CoRR, 2023)

An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique. - Ying Liu 069; Yufei Ma 002; Wei He; Zhixuan Wang; Linxiao Shen; Jiayoon Ru; Ru Huang 001; Le Ye (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Efficient Aging-Aware Standard Cell Library Characterization Based on Sensitivity Analysis. - Xinfa Zhang; Zuodong Zhang; Yibo Lin; Zhigang Ji; Runsheng Wang; Ru Huang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Hadamard product-based in-memory computing design for floating point neural network training. - Anjunyi Fan; Yihan Fu; Yaoyu Tao; Zhonghua Jin; Haiyue Han; Huiyu Liu; Yaojun Zhang; Bonan Yan; Yuchao Yang 001; Ru Huang 001 (Neuromorph. Comput. Eng., 2023)

Interactive Analog Layout Editing With Instant Placement and Routing Legalization. - Xiaohan Gao; Haoyi Zhang; Mingjie Liu; Linxiao Shen; David Z. Pan; Yibo Lin; Runsheng Wang; Ru Huang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Equiprobability-Based Local Response Surface Method for High-Sigma Yield Estimation With Both High Accuracy and Efficiency. - Xiang Liu; Pengpeng Ren; Hai-Bao Chen; Zhigang Ji; Junhua Liu; Runsheng Wang; Jianfu Zhang 001; Ru Huang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro. - Jiahao Song; Xiyuan Tang; Xin Qiao; Yuan Wang 001; Runsheng Wang; Ru Huang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Experimental investigation of a novel junction-modulated hetero-layer tunnel FET with the striped gate for low power applications. - Zhongxin Liang; Yang Zhao; Kaifeng Wang; Jieyin Zhang; Jianjun Zhang; Ming Li; Ru Huang 001; Qianqian Huang (Sci. China Inf. Sci., 2023)

Extremely-Fast, Energy-Efficient Massive MIMO Precoding With Analog RRAM Matrix Computing. - Pushen Zuo; Zhong Sun; Ru Huang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Neuromorphic Artificial Vision Systems Based on Reconfigurable Ion-Modulated Memtransistors. - Zhen Yang; Teng Zhang; Keqin Liu; Bingjie Dang; Liying Xu; Yuchao Yang 001; Ru Huang 001 (Adv. Intell. Syst., 2023)

Memristive dynamics enabled neuromorphic computing systems. - Bonan Yan; Yuchao Yang 001; Ru Huang 001 (Sci. China Inf. Sci., 2023)

Research progress on low-power artificial intelligence of things (AIoT) chip design. - Le Ye; Zhixuan Wang; Tianyu Jia; Yufei Ma 002; Linxiao Shen; Yihan Zhang 002; Heyi Li; Peiyu Chen; Meng Wu 005; Ying Liu 069; Yiqi Jing; Hao Zhang 119; et al. (Sci. China Inf. Sci., 2023)

AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing. - Zuodong Zhang; Zizheng Guo; Yibo Lin; Meng Li 004; Runsheng Wang; Ru Huang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications With Improved Domain-Specific Evaluation Metric and Learning Strategies. - Zhuomin Chai; Yuxiang Zhao; Wei Liu 160; Yibo Lin; Runsheng Wang; Ru Huang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Statistical Compact Modeling With Artificial Neural Networks. - Wu Dai; Yu Li; Zhao Rong; Baokang Peng; Lining Zhang; Runsheng Wang; Ru Huang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

An 8b 1GS/s SAR ADC with Metastability-Based Resolution/Speed Enhancement and Self-Tuning Delay Achieving 47.2dB SNDR at Nyquist Input. - Jie Li; Linxiao Shen; Siyuan Ye; Jihang Gao; Jiajia Cui; Xinhang Xu; Zhuoyi Chen; Yaohui Luan; Yuanxin Bao; Ru Huang 001; Le Ye (CICC, 2024)

Quartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less Dataflow. - Yikan Qiu; Yufei Ma 002; Meng Wu 005; Yifan Jia 009; Xinyu Qu; Zecheng Zhou; Jincheng Lou; Tianyu Jia; Le Ye; Ru Huang 001 (CICC, 2024)

S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications. - Meng Wu 005; Wenjie Ren; Peiyu Chen; Wentao Zhao; Yiqi Jing; Jiayoon Ru; Zhixuan Wang; Yufei Ma 002; Ru Huang 001; Tianyu Jia; Le Ye (CICC, 2024)

An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology. - Zhiyuan Chen 009; Yufei Ma 002; Keyi Li; Yifan Jia 009; Guoxiang Li; Meng Wu 005; Tianyu Jia; Le Ye; Ru Huang 001 (DAC, 2024)

PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning. - Yufan Du; Zizheng Guo; Xun Jiang 002; Zhuomin Chai; Yuxiang Zhao; Yibo Lin; Runsheng Wang; Ru Huang 001 (DAC, 2024)

AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration. - Yiqi Jing; Meng Wu 005; Jiaqi Zhou; Yiyang Sun; Yufei Ma 002; Ru Huang 001; Tianyu Jia; Le Ye (DAC, 2024)

FastQuery: Communication-efficient Embedding Table Query for Private LLMs inference. - Chenqi Lin; Tianshi Xu; Zebin Yang; Runsheng Wang; Ru Huang 001; Meng Li 004 (DAC, 2024)

Compact and Efficient CAM Architecture through Combinatorial Encoding and Self-Terminating Searching for In-Memory-Searching Accelerator. - Weikai Xu; Jin Luo; Qianqian Huang; Ru Huang 001 (DAC, 2024)

EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration. - Haoyi Zhang; Jiahao Song; Xiaohan Gao; Xiyuan Tang; Yibo Lin; Runsheng Wang; Ru Huang 001 (DAC, 2024)

Heterogeneous Static Timing Analysis with Advanced Delay Calculator. - Zizheng Guo; Tsung-Wei Huang; Zhou Jin 001; Cheng Zhuo; Yibo Lin; Runsheng Wang; Ru Huang 001 (DATE, 2024)

BlockAMC: Scalable In-Memory Analog Matrix Computing for Solving Linear Systems. - Lunshuai Pan; Pushen Zuo; Yubiao Luo; Zhong Sun; Ru Huang 001 (DATE, 2024)

IMCE: An In-Memory Computing and Encrypting Hardware Architecture for Robust Edge Security. - Hanyong Shao; Boyi Fu; Jinghao Yang; Wenpu Luo; Chang Su; Zhiyuan Fu; Kechao Tang; Ru Huang 001 (DATE, 2024)

ASCEND: Accurate yet Efficient End-to-End Stochastic Computing Acceleration of Vision Transformer. - Tong Xie; Yixuan Hu; Renjie Wei; Meng Li 004; Yuan Wang 001; Runsheng Wang; Ru Huang 001 (DATE, 2024)

SAGERoute 2.0: Hierarchical Analog and Mixed Signal Routing Considering Versatile Routing Scenarios. - Haoyi Zhang; Xiaohan Gao; Zilong Shen; Jiahao Song; Xiaoxu Cheng; Xiyuan Tang; Yibo Lin; Runsheng Wang; Ru Huang 001 (DATE, 2024)

Hierarchical Power Co-Optimization and Management for LLM Chiplet Designs. - Yanchi Dong; Xueping Liu; Xiaochen Hao; Yun Liang 001; Ru Huang 001; Le Ye; Tianyu Jia (ICCAD, 2024)

Fusion of Global Placement and Gate Sizing with Differentiable Optimization. - Yufan Du; Zizheng Guo; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICCAD, 2024)

Joint Placement Optimization for Hierarchical Analog/Mixed-Signal Circuits. - Xiaohan Gao; Haoyi Zhang; Bingyang Liu; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICCAD, 2024)

HeteroExcept: A CPU-GPU Heterogeneous Algorithm to Accelerate Exception-aware Static Timing Analysis. - Zizheng Guo; Zuodong Zhang; Wuxi Li; Tsung-Wei Huang; Xizhe Shi; Yufan Du; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICCAD, 2024)

OSCA: End-to-end Serial Stochastic Computing Neural Acceleration with Fine-grained Scaling and Piecewise Activation. - Yixuan Hu; Yikang Jia; Meng Li 004; Yuan Wang 001; Runsheng Wang; Ru Huang 001 (ICCAD, 2024)

MORPH: More Robust ASIC Placement for Hybrid Region Constraint Management. - Jing Mai; Zuodong Zhang; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICCAD, 2024)

ATPlace2.5D: Analytical Thermal-Aware Chiplet Placement Framework for Large-Scale 2.5D-IC. - Qipan Wang; Xueqing Li; Tianyu Jia; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICCAD, 2024)

MCUBERT: Memory-Efficient BERT Inference on Commodity Microcontrollers. - Zebin Yang; Renze Chen; Taiqiang Wu; Ngai Wong 001; Yun Liang 001; Runsheng Wang; Ru Huang 001; Meng Li 004 (ICCAD, 2024)

Enforcing hard constraints in physics-informed learning for transient TSV electromigration analysis. - Xiaoman Yang; Hai-Bao Chen; Wenjie Zhu; Yuhan Zhang 005; Yongkang Xue; Pengpeng Ren; Runsheng Wang; Zhigang Ji; Ru Huang 001 (ICCAD, 2024)

FlexHE: A flexible Kernel Generation Framework for Homomorphic Encryption-Based Private Inference. - Jiangrui Yu; Wenxuan Zeng; Tianshi Xu; Renze Chen; Yun Liang 001; Runsheng Wang; Ru Huang 001; Meng Li 004 (ICCAD, 2024)

AdapMoE: Adaptive Sensitivity-based Expert Gating and Management for Efficient MoE Inference. - Shuzhang Zhong; Ling Liang; Yuan Wang 001; Runsheng Wang; Ru Huang 001; Meng Li 004 (ICCAD, 2024)

ProPD: Dynamic Token Tree Pruning and Generation for LLM Parallel Decoding. - Shuzhang Zhong; Zebin Yang; Ruihao Gong; Runsheng Wang; Ru Huang 001; Meng Li 004 (ICCAD, 2024)

FaStTherm: Fast and Stable Full-Chip Transient Thermal Predictor Considering Nonlinear Effects. - Tianxiang Zhu; Qipan Wang; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICCAD, 2024)

CircuitNet 2.0: An Advanced Dataset for Promoting Machine Learning Innovations in Realistic Chip Design Environment. - Xun Jiang 002; Zhuomin Chai; Yuxiang Zhao; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICLR, 2024)

Invited Paper: Design of an RRAM In-Memory Computing Scheme for Target Tracking Applications. - Haoyang Gu; Zongwei Wang 001; Jinshan Li; Hao Ding; Linbo Shan; Lin Bao; Ling Liang; Yimao Cai; Ru Huang 001 (ICTA, 2024)

Accelerating Device-Circuit Self-Heating Simulations with Dynamic Time Evolution for GAAFET. - Sihao Chen; Yu Li; Baokang Peng; Zixuan Sun; Lining Zhang; Runsheng Wang; Ru Huang 001 (IRPS, 2024)

ASAP: An Efficient and Reliable Programming Algorithm for Multi-level RRAM Cell. - Jingwei Sun; Zongwei Wang 001; Jiajun Gao; Linbo Shan; Qishen Wang; Yuhang Yang; Yimao Cai; Ru Huang 001 (IRPS, 2024)

Investigation of Interplays between Body Biasing and Hot Carrier Degradation (HCD) in Advanced NMOS FinFETs. - Zixuan Sun; Yongkang Xue; Haoran Lu; Pengpeng Ren; Zirui Wang; Zhigang Ji; Runsheng Wang; Ru Huang 001 (IRPS, 2024)

New Insights into the Random Telegraph Noise (RTN) in FinFETs at Cryogenic Temperature. - Zirui Wang; Haoran Wang; Yuxiao Wang; Zixuan Sun; Lang Zeng; Runsheng Wang; Ru Huang 001 (IRPS, 2024)

Sub-20-nm DRAM Technology under Negative Bias Temperature Instability (NBTI): from Characterization to Physical Origin Identification. - Da Wang; Yongkang Xue; Yong Liu; Pengpeng Ren; Zixuan Sun; Zirui Wang; Yueyang Liu; Zhijun Cheng; Haiyang Yang; Xiangli Liu; Blacksmith Wu; Kanyu Cao; et al. (IRPS, 2024)

Convolution-Based Vth Shift Prediction and the New 9T2C Pixel Circuit in LTPS TFT AMOLED. - Shiyu Xia; Longda Zhou; Kewei Wang 008; Xiaobin Fan; Yongkang Xue; Qi Shan; Hannian Wang; Pengpeng Ren; Zhigang Ji; Ru Huang 001 (IRPS, 2024)

Investigation of Positive Bias Temperature Instability in advanced FinFET nodes. - Yongkang Xue; Miaojia Yuan; Yu Li; Da Wang; Maokun Wu; Pengpeng Ren; Lining Zhang; Runsheng Wang; Zhigang Ji; Ru Huang 001 (IRPS, 2024)

9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique. - Zhuoyi Chen; Linxiao Shen; Siyuan Ye; Jihang Gao; Jie Li; Jiajia Cui; Xinhang Xu; Yaohui Luan; Hao Zhang 119; Le Ye; Ru Huang 001 (ISSCC, 2024)

30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing. - Ying Liu 069; Yufei Ma 002; Ninghui Shang; Tianhao Zhao; Peiyu Chen; Meng Wu 005; Jiayoon Ru; Tianyu Jia; Le Ye; Zhixuan Wang; Ru Huang 001 (ISSCC, 2024)

30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing. - Jiahao Song; Zihan Wu 005; Xiyuan Tang; Bocheng Xu; Haoyang Luo; Youming Yang 002; Yuan Wang 001; Runsheng Wang; Ru Huang 001 (ISSCC, 2024)

3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS. - Xinhang Xu; Siyuan Ye; Yaohui Luan; Jihang Gao; Jie Li; Jiajia Cui; Hao Zhang 119; Ru Huang 001; Linxiao Shen; Le Ye (ISSCC, 2024)

9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting. - Siyuan Ye; Linxiao Shen; Jihang Gao; Jie Li; Zhuoyi Chen; Xinhang Xu; Jiajia Cui; Hao Zhang 119; Xing Zhang 002; Le Ye; Ru Huang 001 (ISSCC, 2024)

Hestia: An Efficient Cross-Level Debugger for High-Level Synthesis. - Ruifan Xu; Jin Luo; Yawen Zhang; Yibo Lin; Runsheng Wang; Ru Huang 001; Yun Liang 001 (MICRO, 2024)

A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup. - Yanchi Dong; Xueping Liu; Kangbo Bai; Guoxiang Li; Meng Wu 005; Yiqi Jing; Yihan Zhang 002; Pixian Zhan; Yadong Zhang; Yufei Ma 002; Ru Huang 001; Le Ye; et al. (VLSI Technology and Circuits, 2024)

First Experimental Demonstration of Self-Aligned Flip FET (FFET): A Breakthrough Stacked Transistor Technology with 2.5T Design, Dual-Side Active and Interconnects. - Haoran Lu; Yandong Ge; Xun Jiang 002; Jiacheng Sun; Wanyue Peng; Rui Guo; Ming Li; Yibo Lin; Runsheng Wang; Heng Wu 007; Ru Huang 001 (VLSI Technology and Circuits, 2024)

Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

Erratum to: Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

Post-layout simulation driven analog circuit sizing. - Xiaohan Gao; Haoyi Zhang; Siyuan Ye; Mingjie Liu; David Z. Pan; Linxiao Shen; Runsheng Wang; Yibo Lin; Ru Huang 001 (Sci. China Inf. Sci., 2024)

An isolated symmetrical 2T2R cell enabling high precision and high density for RRAM-based in-memory computing. - Yaotian Ling; Zongwei Wang 001; Yuhang Yang; Lin Bao; Shengyu Bao; Qishen Wang; Yimao Cai; Ru Huang 001 (Sci. China Inf. Sci., 2024)

Tuning the ferroelectricity of Hf0.5Zr0.5O2 with alloy electrodes. - Keqin Liu; Bingjie Dang; Zhiyu Yang; Teng Zhang; Zhen Yang; Jinxuan Bai; Zelun Pan; Ru Huang 001; Yuchao Yang 001 (Sci. China Inf. Sci., 2024)

Hole mobility enhancement in monolayer WSe2 p-type transistors through molecular doping. - Shiyuan Liu; Xiong Xiong; Xin Wang 031; Xinhang Shi; Ru Huang 001; Yanqing Wu (Sci. China Inf. Sci., 2024)

Investigation and mitigation of Mott neuronal oscillation fluctuation in spiking neural network. - Lindong Wu; Zongwei Wang 001; Lin Bao; Linbo Shan; Zhizhen Yu; Yunfan Yang; Shuangjie Zhang; Guandong Bai; Cuimei Wang; John Robertson; Yuan Wang 001; Yimao Cai; et al. (Sci. China Inf. Sci., 2024)

AttentionLego: An Open-Source Building Block For Spatially-Scalable Large Language Model Accelerator With Processing-In-Memory Technology. - Rongqing Cong; Wenyang He; Mingxuan Li; Bangning Luo; Zebin Yang; Yuchao Yang 001; Ru Huang 001; Bonan Yan (CoRR, 2024)

Efficient yet Accurate End-to-End SC Accelerator Design. - Meng Li 004; Yixuan Hu; Tengyu Zhang; Renjie Wei; Yawen Zhang; Ru Huang 001; Runsheng Wang (CoRR, 2024)

FastQuery: Communication-efficient Embedding Table Query for Private LLM Inference. - Chenqi Lin; Tianshi Xu; Zebin Yang; Runsheng Wang; Ru Huang 001; Meng Li 004 (CoRR, 2024)

LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design. - Bingyang Liu; Haoyi Zhang; Xiaohan Gao; Zichen Kong; Xiyuan Tang; Yibo Lin; Runsheng Wang; Ru Huang 001 (CoRR, 2024)

The Exploration-Exploitation Dilemma Revisited: An Entropy Perspective. - Renye Yan; Yaozhong Gan; You Wu; Ling Liang; Junliang Xing; Yimao Cai; Ru Huang 001 (CoRR, 2024)

A 0.39-mm2 Stacked Standard-CMOS Humidity Sensor Using a Charge-Redistribution Correlated Level Shifting Floating Inverter Amplifier and a VCO-Based Zoom CDC. - Heyi Li; Kaixuan Du; Yuanxin Bao; Yanchi Dong; Jiayoon Ru; Han Xiao 006; Hao Zhang 119; Zhixuan Wang; Yi Zhong; Linxiao Shen; Le Ye; Ru Huang 001 (IEEE J. Solid State Circuits, 2024)

Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip. - Junjie Wang 008; Teng Zhang; Shuang Liu 007; Yihe Liu; Yuancong Wu; Shaogang Hu; Tupei Chen; Yang Liu 062; Yuchao Yang 001; Ru Huang 001 (IEEE J. Solid State Circuits, 2024)

Probabilistic Compute-in-Memory Design for Efficient Markov Chain Monte Carlo Sampling. - Yihan Fu; Daijing Shi; Anjunyi Fan; Wenshuo Yue; Yuchao Yang 001; Ru Huang 001; Bonan Yan (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM. - Jiahao Song; Xiyuan Tang; Haoyang Luo; Haoyi Zhang; Xin Qiao; Zixuan Sun; Xiangxing Yang; Zihan Wu 005; Yuan Wang 001; Runsheng Wang; Ru Huang 001 (IEEE J. Solid State Circuits, 2024)

Dynamic Supply Noise Aware Timing Analysis With JIT Machine Learning Integration. - Yufei Chen 007; Zizheng Guo; Runsheng Wang; Ru Huang 001; Yibo Lin; Cheng Zhuo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

DRGA-Based Second-Order Block Arnoldi Method for Model Order Reduction of MIMO RCS Circuits. - Hai-Bao Chen; Xinjie Zhang; Wenjie Zhu; Jie Chen 005; Pengpeng Ren; Zhigang Ji; Junhua Liu; Runsheng Wang; Ru Huang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network. - Ying Liu 069; Zhiyuan Chen 009; Wentao Zhao; Tianhao Zhao; Tianyu Jia; Zhixuan Wang; Ru Huang 001; Le Ye; Yufei Ma 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

DCIM-GCN: Digital Computing-in-Memory Accelerator for Graph Convolutional Network. - Yufei Ma 002; Yikan Qiu; Wentao Zhao; Guoxiang Li; Meng Wu 005; Tianyu Jia; Le Ye; Ru Huang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

An RRAM-Based Hierarchical Computing-in-Memory Architecture With Synchronous Parallelism for 3-D Point Cloud Recognition. - Yaotian Ling; Zongwei Wang 001; Lindong Wu; Yimao Cai; Ru Huang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 266F2 Ultra Stable Differential NOR-Structured Physically Unclonable Function With < 6x10-9 Bit Error Rate Through Efficient Redundancy Strategy. - Haoyi Zhang; Jiahao Song; Haoyang Luo; Xiyuan Tang; Yuan Wang 001; Runsheng Wang; Ru Huang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Exploring Better Intra-Cell Routability for Layout Synthesis of Multi-Row Standard Cells. - Kairong Guo; Xiaohan Gao; Haoyi Zhang; Runsheng Wang; Ru Huang 001; Yibo Lin (ASP-DAC, 2025)

A 110µW 99.5dB-SNDR 20kHz-BW Intrinsically Linear CTDSM with Hybrid Gm-Boosting OTA and Tri-Level FIR DACs. - Xinhang Xu; Yaohui Luan; Jie Li; Jihang Gao; Kwok Cheong Li; Jiajia Cui; Ru Huang 001; Linxiao Shen (CICC, 2025)

A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-Sided Signals. - Haoran Lu; Xun Jiang 002; Yanbang Chu; Ziqiao Xu; Rui Guo; Wanyue Peng; Yibo Lin; Runsheng Wang; Heng Wu 007; Ru Huang 001 (DATE, 2025)

Handling Latch Loops in Timing Analysis with Improved Complexity and Divergent Loop Detection. - Xizhe Shi; Zizheng Guo; Yibo Lin; Runsheng Wang; Ru Huang 001 (DATE, 2025)

SCALES: Boost Binary Neural Network for Image Super-Resolution with Efficient Scalings. - Renjie Wei; Zechun Liu; Yuchen Fan; Runsheng Wang; Ru Huang 001; Meng Li 004 (DATE, 2025)

Compact Non-Volatile Lookup Table Architecture Based on Ferroelectric FET Array Through In-Situ Combinatorial One-Hot Encoding for Reconfigurable Computing. - Weikai Xu; Meng Li 004; Qianqian Huang; Ru Huang 001 (DATE, 2025)

FLASH: An Efficient Hardware Accelerator Leveraging Approximate and Sparse FFT for Homomorphic Encryption. - Tengyu Zhang; Yufei Xue; Ling Liang; Zhen Gu; Yuan Wang 001; Runsheng Wang; Ru Huang 001; Meng Li 004 (DATE, 2025)

Leveraging Compute-in-Memory for Efficient Generative Model Inference in TPUs. - Zhantong Zhu; Hongou Li; Wenjie Ren; Meng Wu 005; Le Ye; Ru Huang 001; Tianyu Jia (DATE, 2025)

MORE-Stress: Model Order Reduction based Efficient Numerical Algorithm for Thermal Stress Simulation of TSV Arrays in 2.5D/3D IC. - Tianxiang Zhu; Qipan Wang; Yibo Lin; Runsheng Wang; Ru Huang 001 (DATE, 2025)

Investigation and Mitigation of Transistor Induced Reliability Issues in 40NM RRAM Array. - Yuhang Yang; Zongwei Wang 001; Haoran Wang; Lin Bao; Gaoqi Yang; Yimao Cai; Ru Huang 001 (IRPS, 2025)

SA-CIM: A 28nm 16Mb RRAM-based Sparsity-Aware Compute-In-Memory Macro for Edge AI Algorithm Processing. - Hao Ding; Zongwei Wang 001; Jinshan Li; Shigeng Zhao; Heting Gao; Junbo Ao; Ling Liang; Yimao Cai; Ru Huang 001 (ISCAS, 2025)

HRC-CIM: Hybrid RRAM-Capacitor Cell based Compute-in-Memory with High Linearity, Parallelism and Energy Efficiency. - Jinshan Li; Zongwei Wang 001; Hao Ding; Yunfan Yang; Shigeng Zhao; Shengyu Bao; Jingwei Sun; Ruiqing Xie; Zhuoya Chen; Yimao Cai; Ru Huang 001 (ISCAS, 2025)

LayoutCopilot: LLM-Empowered Analog Layout Design towards Enhanced Human-Machine Interaction. - Bingyang Liu; Haoyi Zhang; Xiaohan Gao; Xiyuan Tang; Yibo Lin; Runsheng Wang; Ru Huang 001 (ISCAS, 2025)

LEGALM: Efficient Legalization for Mixed-Cell-Height Circuits with Linearized Augmented Lagrangian Method. - Jing Mai; Chunyuan Zhao; Zuodong Zhang; Zhixiong Di; Yibo Lin; Runsheng Wang; Ru Huang 001 (ISPD, 2025)

An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input-Buffer-Sampling Scheme and Fast Robust Background Inter-Stage Gain Calibration. - Zhuoyi Chen; Siyuan Ye; Jihang Gao; Jie Li; Jiajia Cui; Xinhang Xu; Yaohui Luan; Ru Huang 001; Linxiao Shen (ISSCC, 2025)

18.3: A 93.3dB SNDR, 180.4dB FoMs Calibration-Free Noise-Shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch-Error-Shaping Technique and Negative-R-Assisted Residue Integrator. - Jihang Gao; Yaohui Luan; Siyuan Ye; Xinhang Xu; Zhuoyi Chen; Jiajia Cui; Ru Huang 001; Linxiao Shen (ISSCC, 2025)

37.6 A 22nm 60.81TFLOPS/W Diffusion Accelerator with Bandwidth-Aware Memory Partition and BL-Segmented Compute-in-Memory for Efficient Multi-Task Content Generation. - Yiqi Jing; Jiaqi Zhou; Yiyang Sun; Siyuan He; Peiyu Chen; Ru Huang 001; Le Ye; Tianyu Jia (ISSCC, 2025)

13.1 A 0.22mm2 161nW Noise-Robust Voice-Activity Detection Using Information-Aware Data Compression and Neuromorphic Spatial-Temporal Feature Extraction. - Ying Liu 069; Jie Li; Qining Zhang; Tianhao Zhao; Chenhao Shi; Ninghui Shang; Peiyu Chen; Xiaohuan Ge; Yufei Ma 002; Linxiao Shen; Zhixuan Wang; Ru Huang 001; et al. (ISSCC, 2025)

18.2 A 12.2μW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD ΔΣM with Gain-Embedded Bootstrapped Sampler. - Yaohui Luan; Xinhang Xu; Jihang Gao; Jiajia Cui; Zhuoyi Chen; Siyuan Ye; Ru Huang 001; Linxiao Shen (ISSCC, 2025)

18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting. - Siyuan Ye; Jiajia Cui; Jihang Gao; Jie Li; Xing Zhang 002; Ru Huang 001; Linxiao Shen (ISSCC, 2025)

Smaller, faster, lower-power analog RRAM matrix computing circuits without performance compromise. - Yubiao Luo; Pushen Zuo; Shiqing Wang; Zhong Sun; Ru Huang 001 (Sci. China Inf. Sci., 2025)

A 28-nm 28.8-TOPS/W Attention-Based NN Processor With Correlative CIM Ring Architecture and Dataflow-Reshaped Digital-Assisted CIM Array. - Ruiqi Guo; Zhiheng Yue; Yang Wang 089; Hao Li; Te Hu; Yabing Wang; Hao Sun; Jeng-Long Hsu; Yaojun Zhang; Bonan Yan; Leibo Liu; Ru Huang 001; et al. (IEEE J. Solid State Circuits, 2025)

An Energy-Efficient, High-Resolution kT/C-Noise- Canceled Pipelined-SAR Capacitance-to-Digital Converter With Incomplete-Settling-Based Correlated Level Shifting in 22-nm CMOS. - Jihang Gao; Siyuan Ye; Jie Li; Xinhang Xu; Zhuoyi Chen; Jiajia Cui; Yaohui Luan; Ru Huang 001; Le Ye; Linxiao Shen (IEEE J. Solid State Circuits, 2025)

PAICORE: A 1.9-Million-Neuron 5.181-TSOPS/W Digital Neuromorphic Processor With Unified SNN-ANN and On-Chip Learning Paradigm. - Yi Zhong; Yisong Kuang; Kefei Liu 002; Zilin Wang; Shuo Feng; Guang Chen; Youming Yang 002; Xiuping Cui; Qiankun Wang; Jian Cao 002; Song Jia; Yun Liang 001; et al. (IEEE J. Solid State Circuits, 2025)

DSTC: Dual-Side Sparse Tensor Core for DNNs Acceleration on Modern GPU Architectures. - Chen Zhang 001; Yang Wang 053; Zhiqiang Xie; Cong Guo 003; Yunxin Liu 001; Jingwen Leng; Zhigang Ji; Yuan Xie 001; Ru Huang 001 (IEEE Trans. Computers, 2025)

A Flying-Capacitor-Based Reset Scheme for Low Power Dynamic Comparator. - Kwok Cheong Li; Xinhang Xu; Jihang Gao; Siyuan Ye; Jiajia Cui; Yacong Zhang; Ru Huang 001; Linxiao Shen (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis. - Xun Jiang 002; Haoran Lu; Yuxuan Zhao 001; Jiarui Wang; Zizheng Guo; Heng Wu 007; Bei Yu 001; Sung Kyu Lim; Runsheng Wang; Ru Huang 001; Yibo Lin (CoRR, 2025)

ReaLM: Reliable and Efficient Large Language Model Inference with Statistical Algorithm-Based Fault Tolerance. - Tong Xie; Jiawang Zhao; Zishen Wan; Zuodong Zhang; Yuan Wang 001; Runsheng Wang; Ru Huang 001; Meng Li 004 (CoRR, 2025)

Physics-Informed Learning Based Multiphysics Simulation for Fast Transient TSV Electromigration Analysis. - Xiaoman Yang; Haibao Chen; Yuhan Zhang 005; Tianshu Hou; Pengpeng Ren; Runsheng Wang; Zhigang Ji; Ru Huang 001 (ACM Trans. Design Autom. Electr. Syst., 2025)

HybriMoE: Hybrid CPU-GPU Scheduling and Cache Management for Efficient MoE Inference. - Shuzhang Zhong; Yanfan Sun; Ling Liang; Runsheng Wang; Ru Huang 001; Meng Li 004 (CoRR, 2025)

UniCAIM: A Unified CAM/CIM Architecture with Static-Dynamic KV Cache Pruning for Efficient Long-Context LLM Inference. - Weikai Xu; Wenxuan Zeng; Qianqian Huang; Meng Li 004; Ru Huang 001 (CoRR, 2025)

EdgeMM: Multi-Core CPU with Heterogeneous AI-Extension and Activation-aware Weight Pruning for Multimodal LLMs at Edge. - Kangbo Bai; Le Ye; Ru Huang 001; Tianyu Jia (CoRR, 2025)

PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction. - Yuxiang Zhao; Zhuomin Chai; Xun Jiang 002; Yibo Lin; Runsheng Wang; Ru Huang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

SpecASR: Accelerating LLM-based Automatic Speech Recognition via Speculative Decoding. - Linye Wei; Shuzhang Zhong; Songqiang Xu; Runsheng Wang; Ru Huang 001; Meng Li 004 (CoRR, 2025)

A 2-mW 70.7-dB SNDR 200-MS/s Pipelined-SAR ADC Using Continuous-Time SAR-Assisted Detect-and-Skip and Open-Then-Close Correlated Level Shifting. - Siyuan Ye; Jihang Gao; Jie Li; Zhuoyi Chen; Xinhang Xu; Jiajia Cui; Yaohui Luan; Le Ye; Xing Zhang 002; Ru Huang 001; Linxiao Shen (IEEE J. Solid State Circuits, 2025)

Fine-Grained Structured Sparse Computing for FPGA-Based AI Inference. - Chen Zhang 001; Shijie Cao; Guohao Dai; Chenbo Geng; Zhuliang Yao; Wencong Xiao; Yunxin Liu 001; Ming Wu 007; Lintao Zhang; Guangyu Sun 003; Zhigang Ji; Runsheng Wang; et al. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

A 22-nm Delta-Sigma Computing-In-Memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing. - Peiyu Chen; Wentao Zhao; Meng Wu 005; Linxiao Shen; Tianyu Jia; Ru Huang 001; Le Ye; Yufei Ma 002 (IEEE J. Solid State Circuits, 2025)

LayoutCopilot: An LLM-Powered Multiagent Collaborative Framework for Interactive Analog Layout Design. - Bingyang Liu; Haoyi Zhang; Xiaohan Gao; Zichen Kong; Xiyuan Tang; Yibo Lin; Runsheng Wang; Ru Huang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)