A Novel Multi-Bit Sigma-Delta Modulator using an Integrating SAR Noise-Shaped Quantizer. - Rubén Garvi; Enrique Prefasi (ICECS, 2018)

A 1-1 MASH using two Noise-Shaping Switched-Capacitor Dual-Slope converters. - Christopher Rogi; Rubén Garvi; Enrique Prefasi (PRIME, 2019)

VCO-ADC Linearization by Switched Capacitor Frequency-to-Current Conversion. - Rubén Garvi; Leidy Mabel Alvero-Gonzalez; Carlos Perez; Eric Gutierrez; Luis Hernández 003 (ISCAS, 2020)

A 55nm CMOS Linearized Oscillator for Audio VCO-ADCs achieving 78dBA of SNDR with $153 mu mathrm{W}$. - Rubén Garvi; Javier Granizo; Angel Salvador; Luis Hernández 003 (ICECS 2022, 2022)

A Phase-Encoded Voice Features Extraction Circuit Using Digital Mixers and Analog Filters based on Ring Oscillators. - Rubén Garvi; Eric Gutierrez; Victor Medina; Luis Hernández 003 (ISCAS, 2022)

A maximally-digital VCO-ADC with inherent mixing input capability. - Victor Medina; Rubén Garvi; Eric Gutierrez; Luis Hernández 003 (ISCAS, 2022)

A CMOS LIF neuron based on a charge-powered oscillator with time-domain threshold logic. - Javier Granizo; Rubén Garvi; Diego Garcia; Luis Hernández 003 (ISCAS, 2023)

A Gray-Encoded Ring Oscillator for Efficient Frequency-to-Digital Conversion in VCO-Based ADCs. - Victor Medina; Rubén Garvi; Eric Gutierrez; Susana Patón; Luis Hernández 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A VCO-ADC Linearized by a Capacitive Frequency-to-Current Converter. - Rubén Garvi; Javier Granizo; Eric Gutierrez; Victor Medina; Andreas Wiesbauer; Luis Hernández 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A VCO-Based ADC With Inherent Mixing Capability and Local Oscillator Suppression in 55-nm CMOS. - Victor Medina; Rubén Garvi; Eric Gutierrez; Luis Hernández 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

System Analysis of Capacitance-to-Digital Converters Based on a Switched-Capacitor Feedback. - Michele Noviello; Rubén Garvi; Andrés Quintero; Susana Patón (MWSCAS, 2024)

A Second-Order Audio VCO-ADC with 103-dB-A Dynamic Range and Binary-Weighted Internal Architecture. - Victor Medina; Rubén Garvi; Javier Granizo; Pedro Amaral; Luis Hernández 003 (CoRR, 2024)

Analysis of Clock Jitter in VCO-ADCs Under Presence of Mismatch and Blocking Signals. - Javier Granizo; Victor Medina; Luis Hernández 003; Rubén Garvi (ISCAS, 2025)

Second-Order VCO-ADC Architecture With Low-Area and High Dynamic Range Using Internal Binary Encoding. - Victor Medina; Rubén Garvi; Javier Granizo; Pedro Amaral; Luis Hernandez Corporales (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)