A Content Aware Integer Register File Organization. - Rubén González 001; Adrián Cristal; Daniel Ortega; Alexander V. Veidenbaum; Mateo Valero (ISCA, 2004)

An Optimized Front-End Physical Register File with Banking and Writeback Filtering. - Miquel Pericàs; Rubén González 001; Adrián Cristal; Alexander V. Veidenbaum; Mateo Valero (PACS, 2004)

An asymmetric clustered processor based on value content. - Rubén González 001; Adrián Cristal; Miquel Pericàs; Mateo Valero; Alexander V. Veidenbaum (ICS, 2005)

Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor. - Miquel Pericàs; Adrián Cristal; Rubén González 001; Daniel A. Jiménez; Mateo Valero (ISHPC, 2005)

Decoupled State-Execute Architecture. - Miquel Pericàs; Adrián Cristal; Rubén González 001; Alexander V. Veidenbaum; Mateo Valero (ISHPC, 2005)

Chained In-Order/Out-of-Order DoubleCore Architecture. - Miquel Pericàs; Adrián Cristal; Rubén González 001; Daniel A. Jiménez (SBAC-PAD, 2005)

A decoupled KILO-instruction processor. - Miquel Pericàs; Adrián Cristal; Rubén González 001; Daniel A. Jiménez; Mateo Valero (HPCA, 2006)

DRAP: Dual-queue rate-controlled access point for multimedia communications in WLAN hotspots. - Rubén González 001; Llorenç Cerdà (Communication Systems and Networks, 2006)

A Flexible Heterogeneous Multi-Core Architecture. - Miquel Pericàs; Adrián Cristal; Francisco J. Cazorla; Rubén González 001; Daniel A. Jiménez; Mateo Valero (PACT, 2007)

A Two-Level Load/Store Queue Based on Execution Locality. - Miquel Pericàs; Adrián Cristal; Francisco J. Cazorla; Rubén González 001; Alexander V. Veidenbaum; Daniel A. Jiménez; Mateo Valero (ISCA, 2008)