Design methodology and microdiagnostics development for a self-checking microprocessor. - Rubin A. Parekhji; N. K. Nanda (MICRO, 1989)

A Methodology for Designing Optimal Self-Checking Sequential Circuits. - Rubin A. Parekhji; G. Venkatesh 001; Sunil D. Sherlekar (ITC, 1991)

State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits. - Rubin A. Parekhji; G. Venkatesh 001; Sunil D. Sherlekar (VLSI Design, 1993)

A new methodology for the design of low-cost fail safe circuits and networks. - B. Ravi Kishore; Rubin A. Parekhji; Sandeep Pagey; Sunil D. Sherlekar; G. Venkatesh 001 (VLSI Design, 1995)

Concurrent Error Detection Using Monitoring Machines. - Rubin A. Parekhji; G. Venkatesh 001; Sunil D. Sherlekar (IEEE Des. Test Comput., 1995)

E-Groups: A New Technique for Fast Backward Propagation in System Level Test Generation. - Michael Nicolaidis; Rubin A. Parekhji; M. Boudjit (Asian Test Symposium, 1996)

Monitoring machine based synthesis technique for concurrent error detection in finite state machines. - Rubin A. Parekhji; G. Venkatesh 001; Sunil D. Sherlekar (J. Electron. Test., 1996)

Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems. - Ameet Bagwe; Rubin A. Parekhji (Asian Test Symposium, 2000)

A framework to evaluate test tradeoffs in embedded core based systems-case study on TI's TMS320C27xx. - Jais Abraham; Narayan Prasad; Srinivasa Chakravarthy B. S.; Ameet Bagwe; Rubin A. Parekhji (ITC, 2000)

Test Techniques and Trade-offs for Embedded Cores and Systems. - Rubin A. Parekhji (VLSI Design, 2000)

Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. - Karanth Shankaranarayana; Soujanna Sarkar; R. Venkatraman; Shyam S. Jagini; N. Venkatesh; Jagdish C. Rao; H. Udayakumar; M. Sambandam; K. P. Sheshadri; S. Talapatra; Parag Mhatre; Jais Abraham; et al. (ASP-DAC/VLSI Design, 2002)

Panel Synopsis - How (In)Adequate is One Time Testing? - Rubin A. Parekhji (ITC, 2003)

Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions. - Rubin A. Parekhji (VLSI Design, 2003)

CESC: a visual formalism for specification and verification of SoCs. - Ambar A. Gadkari; S. Ramesh 001; Rubin A. Parekhji (ACM Great Lakes Symposium on VLSI, 2004)

DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI's TNETD7300 ADSL Modem Device. - K. Nikila; Rubin A. Parekhji (ITC, 2004)

Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories. - Rajeshwar S. Sable; Ravindra P. Saraf; Rubin A. Parekhji; Arun N. Chandorkar (VLSI Design, 2004)

ITC 2003 panels: Part 1. - Carol Stolicny; Tapio Koivukangas; Rubin A. Parekhji; Ian G. Harris; Rob Aitken (IEEE Des. Test Comput., 2004)

Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency. - Sameer Goel; Rubin A. Parekhji (Asian Test Symposium, 2005)

DFT for Low Cost SOC Test. - Rubin A. Parekhji (Asian Test Symposium, 2005)

On-chip Test and Repair of Memories for Static and Dynamic Faults. - Sanjay K. Thakur; Rubin A. Parekhji; Arun N. Chandorkar (ITC, 2006)

Session Abstract. - Rubin A. Parekhji (VTS, 2006)

Methodology for low power test pattern generation using activity threshold control logic. - Srivaths Ravi 001; V. R. Devanathan; Rubin A. Parekhji (ICCAD, 2007)

Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs. - Sandeep Jain; Jais Abraham; Srinivas Kumar Vooka; Sumant Kale; Amit Dutta; Rubin A. Parekhji (VLSI Design, 2007)

Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs. - Subir K. Roy; Rubin A. Parekhji (VLSI Design, 2007)

Modified Stability Checking for On-line Error Detection. - Satish Yada; Bharadwaj S. Amrutur; Rubin A. Parekhji (VLSI Design, 2007)

Power Analysis and Reduction Techniques for Transition Fault Testing. - Khushboo Agarwal; Srinivas Vooka; Srivaths Ravi 001; Rubin A. Parekhji; Arjun Singh Gill (ATS, 2008)

Evaluation of Entropy Driven Compression Bounds on Industrial Designs. - Srinivasulu Alampally; Jais Abraham; Rubin A. Parekhji; Rohit Kapur; Thomas W. Williams (ATS, 2008)

False Error Study of On-line Soft Error Detection Mechanisms. - M. Kiran Kumar Reddy; Bharadwaj S. Amrutur; Rubin A. Parekhji (IOLTS, 2008)

DFT Implementationis for Striking the Right Balance between Test Cost and Test Quality for Automotive SOCs. - Amit Dutta; Srinivasulu Alampally; V. Prasanth 001; Rubin A. Parekhji (ITC, 2008)

A systematic approach to synthesis of verification test-suites for modular SoC designs. - Sudhakar Surendran; Rubin A. Parekhji; R. Govindarajan (SoCC, 2008)

A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips. - Rajesh Tiwari; Abhijeet Shrivastava; Mahit Warhadpande; Srivaths Ravi 001; Rubin A. Parekhji (VTS, 2008)

Low Power Test for Nanometer System-on-Chips (SoCs). - Srivaths Ravi 001; Rubin A. Parekhji; Jayashree Saxena (J. Low Power Electron., 2008)

Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect Coverage. - Hongxia Fang; Krishnendu Chakrabarty; Rubin A. Parekhji (Asian Test Symposium, 2009)

Design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test. - Amit Dutta; Malav Shah; G. Swathi; Rubin A. Parekhji (IOLTS, 2009)

Robust detection of soft errors using delayed capture methodology. - V. Prasanth 001; Virendra Singh; Rubin A. Parekhji (IOLTS, 2010)

Test time reduction using parallel RF test techniques. - Rajesh Mittal; Adesh Sontakke; Rubin A. Parekhji (VTS, 2010)

Innovative practices session 1C: Innovative practices in RF test. - Rubin A. Parekhji (VTS, 2010)

A generic low power scan chain wrapper for designs using scan compression. - Amit Sabne; Rajesh Tiwari; Abhijeet Shrivastava; Srivaths Ravi 001; Rubin A. Parekhji (VTS, 2010)

False Error Vulnerability Study of On-line Soft Error Detection Mechanisms. - M. Kiran Kumar Reddy; Bharadwaj S. Amrutur; Rubin A. Parekhji (J. Electron. Test., 2010)

Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands. - Xrysovalantis Kavousianos; Krishnendu Chakrabarty; Arvind Jain; Rubin A. Parekhji (Asian Test Symposium, 2011)

Reduced overhead soft error mitigation using error control coding techniques. - V. Prasanth 001; Virendra Singh; Rubin A. Parekhji (IOLTS, 2011)

DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management. - Rajesh Mittal; Lakshmanan Balasubramanian; Adesh Sontakke; Harikrishna Parthasarathy; Prakash Narayanan; Puneet Sabbarwal; Rubin A. Parekhji (ITC, 2011)

Multi-CoDec Configurations for Low Power and High Quality Scan Test. - Arvind Jain; Sundarrajan Subramanian; Rubin A. Parekhji; Srivaths Ravi 001 (VLSI Design, 2011)

An efficient test data reduction technique through dynamic pattern mixing across multiple fault models. - Srinivasulu Alampally; R. T. Venkatesh; Priyadharshini Shanmugasundaram; Rubin A. Parekhji; Vishwani D. Agrawal (VTS, 2011)

Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test. - Arvind Jain; Sundarrajan Subramanian; Rubin A. Parekhji; Srivaths Ravi 001 (J. Low Power Electron., 2011)

Time-division multiplexing for testing SoCs with DVS and multiple voltage islands. - Xrysovalantis Kavousianos; Krishnendu Chakrabarty; Arvind Jain; Rubin A. Parekhji (ETS, 2012)

Derating based hardware optimizations in soft error tolerant designs. - V. Prasanth 001; Virendra Singh; Rubin A. Parekhji (VTS, 2012)

Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands. - Xrysovalantis Kavousianos; Krishnendu Chakrabarty; Arvind Jain; Rubin A. Parekhji (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Towards adaptive test of multi-core RF SoCs. - Rajesh Mittal; Lakshmanan Balasubramanian; Y. B. Chethan Kumar; V. R. Devanathan; Mudasir Kawoosa; Rubin A. Parekhji (DATE, 2013)

Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing. - Fotis Vartziotis; Xrysovalantis Kavousianos; Krishnendu Chakrabarty; Rubin A. Parekhji; Arvind Jain (DATE, 2014)

Systematic approach for trim test time optimization: Case study on a multi-core RF SOC. - Rajesh Mittal; Mudasir Kawoosa; Rubin A. Parekhji (ITC, 2014)

Improved Methods for Accurate Safety Analysis of Real-Life Systems. - V. Prasanth 001; Rubin A. Parekhji; Bharadwaj S. Amrutur (ATS, 2015)

On-chip measurement of bandgap reference voltage using a small form factor VCO based zoom-in ADC. - Osman Emir Erol; Sule Ozev; Chandra K. H. Suresh; Rubin A. Parekhji; Lakshmanan Balasubramanian (DATE, 2015)

New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation. - V. R. Devanathan; Lakshmanan Balasubramanian; Rubin A. Parekhji (VLSID, 2015)

Guest Editors' Introduction: Speeding Up Analog Integration and Test for Mixed-Signal SoCs. - Rubin A. Parekhji; Kenneth Butler; Gordon W. Roberts (IEEE Des. Test, 2015)

Time-Division Multiplexing for Testing DVFS-Based SoCs. - Fotis Vartziotis; Xrysovalantis Kavousianos; Krishnendu Chakrabarty; Arvind Jain; Rubin A. Parekhji (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

A novel technique for interdependent trim code optimization. - Pankaj Bongale; Vinothkumar Sundaresan; Partha Ghosh; Rubin A. Parekhji (VTS, 2016)

Low cost dynamic error detection in linearity testing of SAR ADCs. - Nimit Jain; Nitin Agarwal; Rajavelu Thinakaran; Rubin A. Parekhji (ITC, 2017)

Safety analysis for integrated circuits in the context of hybrid systems. - V. Prasanth 001; Rubin A. Parekhji; Bharadwaj Amrutur (ITC, 2017)

Innovative practices session 2C: "How is industry simplifying analog test". - Rubin A. Parekhji; Srinivas Modekurty (VTS, 2017)

An optimised SDD ATPG and SDQL computation method across different pattern sets. - Wilson Pradeep; Prakash Narayanan; Rubin A. Parekhji (VTS, 2017)

Towards Single Pin Scan for Extremely Low Pin Count Test. - Mudasir S. Kawoosa; Rajesh K. Mittal; Maheedhar Jalasuthram; Rubin A. Parekhji (VLSID, 2018)

Perturbation Based Workload Augmentation for Comprehensive Functional Safety Analysis. - V. Prasanth 001; Rubin A. Parekhji; Bharadwaj Amrutur (VLSID, 2019)

Guest Editorial. - Kanad Basu; Mingsong Chen 001; Rubin A. Parekhji (J. Electron. Test., 2019)

Exploiting Application Tolerance for Functional Safety. - V. Prasanth 001; Rubin A. Parekhji; Bharadwaj Amrutur (ITC, 2021)

Innovative Practices Track: New Methods for System Level Test of Image Projection and Radar VLSI Systems. - Rubin A. Parekhji (VTS, 2022)

Graph Learning-based Fault Criticality Analysis for Enhancing Functional Safety of E/E Systems. - Sanjay Das; Shamik Kundu; Pooja Madhusoodhanan; Viswanathan Pillai Prasanth; Rubin A. Parekhji; Arnab Raha; Suvadeep Banerjee; Suriya Natarajan; Kanad Basu (DAC, 2024)

Hierarchical Fault Simulation for Mixed-Signal Circuits Using Template Based Fault Response Modeling. - Tolga Aksoy; Nikhil Sagar Modala; Lakshmanan Balasubramanian; Rubin A. Parekhji; Sule Ozev (ETS, 2024)

Safety-Guided Test Generation for Structural Faults. - Xuanyi Tan; Dhruv Thapar; Deepesh Sahoo; Arjun Chaudhuri; Sanmitra Banerjee; Krishnendu Chakrabarty; Rubin A. Parekhji (ITC, 2024)

Increasing the Efficiency of Hierarchical Fault Simulation through Functional Fault Clustering. - Nikhil Sagar Modala; Lakshmanan Balasubramanian; Rubin A. Parekhji; Sule Ozev (MWSCAS, 2024)

Enhancing Functional Safety in Automotive AMS Circuits through Unsupervised Machine Learning. - Ayush Arunachalam; Ian Kintz; Suvadeep Banerjee; Arnab Raha; Xiankun Jin; Fei Su; Viswanathan Pillai Prasanth; Rubin A. Parekhji; Suriyaprakash Natarajan; Kanad Basu (CoRR, 2024)

Enhancing AMS Circuit Reliability: An Anomaly Dataset for Functional Safety Research in Automotive SoCs. - Sanjay Das; Anand Menon; Omar Abiola Abioye; Afreen Fatimah Khazi-Syed; Jonathan Edward Lee; Ayush Arunachalam; Shamik Kundu; Pooja Madhusoodhanan; Prasanth Viswanathan Pillai; Rubin A. Parekhji; Arnab Raha; Suvadeep Banerjee; et al. (ACM Great Lakes Symposium on VLSI, 2025)

Defect Severity Analysis for Analog Circuits Using Zoom Search and Hierarchical Fault Simulation. - Mehmet Onder; Lakshmanan Balasubramanian; Rubin A. Parekhji; Suriyaprakash Natarajan; Sule Ozev (VTS, 2025)