A 0.031mm2, 910fs, 0.5-4GHz injection type SOC PLL with 90dB built-in supply noise rejection in 10nm FinFET CMOS. - Chin-Yang Wu; Ruei-Pin Shen; Chih-Hsien Chang; Kenny Hsieh; Mark Chen 001 (CICC, 2017)

A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOS. - Ting-Kuei Kuan; Chin-Yang Wu; Ruei-Pin Shen; Chih-Hsien Chang; Kenny Hsieh; Mark Chen 001 (VLSI Circuits, 2018)

A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS. - Chen-Ting Ko; Ting-Kuei Kuan; Ruei-Pin Shen; Chih-Hsien Chang; Kenny Hsieh; Mark Chen 001 (VLSI Circuits, 2019)

A 7-nm FinFET CMOS PLL With 388-fs Jitter and -80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control. - Chen-Ting Ko; Ting-Kuei Kuan; Ruei-Pin Shen; Chih-Hsien Chang (IEEE J. Solid State Circuits, 2020)