An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics. - Liang-Bi Chen; Ruei-Ting Gu; Wei-Sheng Huang; Chien-Chou Wang; Wen-Chi Shiue; Tsung-Yu Ho; Yun-Nan Chang; Shen-Fu Hsiao; Chung-Nan Lee; Ing-Jer Huang (ASP-DAC, 2009)

A Unified Interconnects Testing Scheme for 3D Integrated Circuits. - Chih-Yun Pai; Ruei-Ting Gu; Bo-Chuan Cheng; Liang-Bi Chen; Katherine Shu-Min Li (Asian Test Symposium, 2011)

A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package. - Katherine Shu-Min Li; Cheng-You Ho; Ruei-Ting Gu; Sying-Jyan Wang; Yingchieh Ho; Jiun-Jie Huang; Bo-Chuan Cheng; An-Ting Liu (Asian Test Symposium, 2013)

Optimized Pre-bond Test Methodology for Silicon Interposer Testing. - Katherine Shu-Min Li; Sying-Jyan Wang; Jia-Lin Wu; Cheng-You Ho; Yingchieh Ho; Ruei-Ting Gu; Bo-Chuan Cheng (ATS, 2014)

Layout-Aware Optimized Prebond Silicon Interposer Test Synthesis. - Katherine Shu-Min Li; Sying-Jyan Wang; Ruei-Ting Gu; Bo-Chuan Cheng (IEEE Des. Test, 2017)