Sinusoidal Clock Sampling for Multigigahertz ADCs. - Rui Bai 001; Jingguang Wang; Lingli Xia; Feng Zhang 014; Zongren Yang; Weiwu Hu; Patrick Chiang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking. - Kangmin Hu; Rui Bai 001; Tao Jiang 005; Chao Ma 020; Ahmed Ragab; Samuel Palermo; Patrick Yin Chiang (IEEE J. Solid State Circuits, 2012)

A ring-resonator-based silicon photonics transceiver with bias-based wavelength stabilization and adaptive-power-sensitivity receiver. - Cheng Li; Rui Bai 001; Ayman Shafik; Ehsan Zhian Tabasy; Geng Tang; Chao Ma 020; Chin-Hui Chen; Zhen Peng; Marco Fiorentino; Patrick Chiang 001; Samuel Palermo (ISSCC, 2013)

A 0.47-0.66 pJ/bit, 4.8-8 Gb/s I/O Transceiver in 65 nm CMOS. - Young-Hoon Song; Rui Bai 001; Kangmin Hu; Noah Hae-Woong Yang; Patrick Yin Chiang; Samuel Palermo (IEEE J. Solid State Circuits, 2013)

2.5 A 0.25pJ/b 0.7V 16Gb/s 3-tap decision-feedback equalizer in 65nm CMOS. - Rui Bai 001; Samuel Palermo; Patrick Yin Chiang (ISSCC, 2014)

A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS. - Hao Li 047; Shuai Chen; Liqiong Yang; Rui Bai 001; Weiwu Hu; Freeman Y. Zhong; Samuel Palermo; Patrick Yin Chiang (VLSIC, 2014)

Silicon Photonic Transceiver Circuits With Microring Resonator Bias-Based Wavelength Stabilization in 65 nm CMOS. - Cheng Li; Rui Bai 001; Ayman Shafik; Ehsan Zhian Tabasy; Binhao Wang; Geng Tang; Chao Ma 020; Chin-Hui Chen; Zhen Peng; Marco Fiorentino; Raymond G. Beausoleil; Patrick Chiang 001; et al. (IEEE J. Solid State Circuits, 2014)

22.4 A 24Gb/s 0.71pJ/b Si-photonic source-synchronous receiver with adaptive equalization and microring wavelength stabilization. - Kunzhi Yu; Hao Li 047; Cheng Li; Alex Titriku; Ayman Shafik; Binhao Wang; Zhongkai Wang; Rui Bai 001; Chin-Hui Chen; Marco Fiorentino; Patrick Yin Chiang; Samuel Palermo (ISSCC, 2015)

A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization. - Kunzhi Yu; Cheng Li; Hao Li 047; Alex Titriku; Ayman Shafik; Binhao Wang; Zhongkai Wang; Rui Bai 001; Chin-Hui Chen; Marco Fiorentino; Patrick Yin Chiang; Samuel Palermo (IEEE J. Solid State Circuits, 2016)

A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects. - Nan Qi; Yuhang Kang; Qipeng Lin; Jianxu Ma; Jingbo Shi; Bozhi Yin; Chang Liu; Rui Bai 001; Shang Hu; Juncheng Wang; Jiangbing Du; Lin Ma 008; et al. (A-SSCC, 2017)

A Fully-Integrated 25Gb/s Low-Noise TIA+CDR Optical Receiver designed in 40nm-CMOS. - Juncheng Wang; Xuefeng Chen 004; Shang Hu; Yaxin Cai; Rui Bai 001; Xin Wang 130; Yuanxi Zhang; Shenglong Zhuo; Chang Liu; Bozhi Yin; Jianxu Ma; Hao Yan; et al. (A-SSCC, 2018)

A 50Gb/s-PAM4 CDR with On-Chip Eye Opening Monitor for Reference-Level and Clock-Sampling Adaptation. - Chang Liu; Bozhi Yin; Tingyu Yao; Nan Qi; Dan Li 011; Jingbo Shi; Juncheng Wang; Hu Shang; Rui Bai 001; Patrick Yin Chiang (OFC, 2018)

A 50Gb/s PAM-4 Retimer-CDR + VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die. - Shang Hu; Tingyu Yao; Bozhi Yin; Chunyu Song; Lei Zhao; Juncheng Wang; Lei Wang 187; Rui Bai 001; Xin Wang 130; Tao Xia; Yi Peng; Binbin Yao; et al. (OFC, 2019)

A Fully Integrated 25 Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40-nm-CMOS. - Juncheng Wang; Quan Pan 002; Yajie Qin; Xuefeng Chen 004; Shang Hu; Rui Bai 001; Xin Wang 130; Yaxin Cai; Tao Xia; Yuanxi Zhang; Jianxu Ma; Nan Qi; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

PAM-X™: A 25Gb/s-PAM4 Optical Transceiver Chipset for 5G Optical Front-Haul. - Xin Wang 130; Yi Peng; Yuanxi Zhang; Tao Xia; Yifan Wu 009; Juncheng Wang; Lei Wang 187; Liujia Song; Lei Zhao; Shenglong Zhuo; Quan Pan 002; Xuefeng Chen 004; et al. (OFC, 2020)

A 4 × 10 Gb/s Adaptive Optical Receiver Utilizing Current-Reuse and Crosstalk-Remove. - Juncheng Wang; Xuefeng Chen 004; Rui Bai 001; Patrick Yin Chiang; Quan Pan 002 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20W/Ch Transmitter, and a 128x128 SPAD Receiver with SNR-Based Pixel Binning and Resolution Upscaling. - Shenglong Zhuo; Lei Zhao; Tao Xia; Lei Wang 187; Shi Shi; Yifan Wu 009; Chang Liu; Chill Wang; Yuwei Wang; Yuan Li; Hengwei Yu; Jiqing Xu; et al. (CICC, 2022)

An Integrated 200MHz 4A Pulsed Laser Driver with DLL-Based Time Interpolator for Indirect Time-of-Flight Applications. - Shenglong Zhuo; Yuwei Wang; Tao Xia; Yifan Wu 009; Lichun Xie; Wei Zheng; Zhihong Lin; Miao Sun; Lei Zhao; Yajie Qin; Rui Bai 001; Patrick Yin Chiang (ISCAS, 2022)

dToF LIDAR System Using Addressable Multi-Channel VCSEL Transmitter, 128x80 SPAD Sensor, and ML-Based Object Detection for Adaptive Beam-Steering. - Yifan Wu 009; Sifan Zhou; Miao Sun; Tao Xia; Jian Qian; Lei Wang 187; Shi Shi; Lebei Cui; Chill Wang; Yuan Li; Hengwei Yu; Zhihong Lin; et al. (CICC, 2023)

Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20-W/Ch Transmitter, and a 128 × 128 SPAD Receiver With SNR-Based Pixel Binning and Resolution Upscaling. - Shenglong Zhuo; Tao Xia; Lei Zhao; Miao Sun; Yifan Wu 009; Lei Wang 187; Hengwei Yu; Jiqing Xu; Jier Wang; Zhihong Lin; Yuan Li; Lei Qiu 002; et al. (IEEE J. Solid State Circuits, 2023)

An Adaptive Beam-Steering dToF LiDAR System Using Addressable Multi-Channel VCSEL Transmitter, 128 × 80 SPAD Sensor, and ML-Based Edge-Computing Object Detection. - Yifan Wu 009; Miao Sun; Sifan Zhou; Tao Xia; Lei Wang 187; Jier Wang; Yuan Li; Ming Zhong; Rui Bai 001; Xuefeng Chen 004; Yuanjin Zheng; Patrick Yin Chiang; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)