Phase Compensation Technique for a Low-Power Transconductor. - Rui Ito; Tetsuro Itakura; Tadashi Arai (IEICE Trans. Electron., 2005)

A Direct Conversion Receiver for W-CDMA Reducing Current Consumption to 31 mA. - Hiroshi Yoshida; Takehiko Toyoda; Makoto Arai; Ryuichi Fujimoto; Toshiya Mitomo; Masato Ishii; Rui Ito; Tadashi Arai; Tetsuro Itakura; Hiroshi Tsurumi (IEICE Trans. Electron., 2005)

Balanced 3-phase analog signal processing for radio communications. - Takafumi Yamaji; Tetsuro Itakura; Rui Ito; Takeshi Ueno; Hidenori Okuni (ISCAS, 2006)

A novel quality factor tuning scheme for active-RC filters. - Shouhei Kousai; Mototsugu Hamada; Rui Ito; Tetsuro Itakura (ESSCIRC, 2007)

A Direct Conversion Receiver with Fast-Settling DC Offset Canceller. - Hidenori Okuni; Rui Ito; Hiroshi Yoshida; Tetsuro Itakura (PIMRC, 2007)

A Fast fc Automatic Tuning Circuit with Wide Tuning Range for WCDMA Direct Conversion Receiver Systems. - Osamu Watanabe 003; Rui Ito; Shigehito Saigusa; Tadashi Arai; Tetsuro Itakura (IEICE Trans. Electron., 2007)

A 19.7 MHz, Fifth-Order Active-RCChebyshev LPF for Draft IEEE802.11n With Automatic Quality-Factor Tuning Scheme. - Shouhei Kousai; Mototsugu Hamada; Rui Ito; Tetsuro Itakura (IEEE J. Solid State Circuits, 2007)

A 1.2V 0.2-to-6.3GHz Transceiver with Less Than -29.5dB EVM@-3dBm and a Choke/Coil-Less Pre-Power Amplifier. - Shouhei Kousai; Daisuke Miyashita; Junji Wadatsumi; Asuka Maki; Takahiro Sekiguchi; Rui Ito; Mototsugu Hamada (ISSCC, 2008)

A Triple-Band WCDMA Direct Conversion Receiver IC with Reduced Number of Off-Chip Components and Digital Baseband Control Signals. - Osamu Watanabe 003; Rui Ito; Toshiya Mitomo; Shigehito Saigusa; Tadashi Arai; Takehiko Toyoda (IEICE Trans. Electron., 2008)

A Novel Automatic Quality Factor Tuning Scheme for a Low-Power Wideband Active-RC Filter. - Shouhei Kousai; Mototsugu Hamada; Rui Ito; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS. - Jun Deguchi; Daisuke Miyashita; Yosuke Ogasawara; Gaku Takemura; Masaomi Iwanaga; Kenichi Sami; Rui Ito; Junji Wadatsumi; Yuki Tsuda; Shoko Oda; Shunji Kawaguchi; Nobuyuki Itoh; et al. (ISSCC, 2010)

Phase Compensation Techniques for Low-Power Operational Amplifiers. - Rui Ito; Tetsuro Itakura (IEICE Trans. Electron., 2010)

A Fully Integrated 2 ˟ 1 Dual-Band Direct-Conversion Mobile WiMAX Transceiver With Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifier in 65 nm CMOS. - Jun Deguchi; Daisuke Miyashita; Yosuke Ogasawara; Gaku Takemura; Masaomi Iwanaga; Kenichi Sami; Rui Ito; Junji Wadatsumi; Yuki Tsuda; Shoko Oda; Shunji Kawaguchi; Nobuyuki Itoh; et al. (IEEE J. Solid State Circuits, 2010)

A Low-Noise and Highly-Linear Transmitter with Envelope Injection Pre-Power Amplifier for Multi-Mode Radio. - Shouhei Kousai; Daisuke Miyashita; Junji Wadatsumi; Rui Ito; Takahiro Sekiguchi; Mototsugu Hamada; Kenichi Okada 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

A low voltage 0.8V RF receiver in 28nm CMOS for 5GHz WLAN. - Atsushi Shirane; Shusuke Kawai; Hiromitsu Aoyama; Rui Ito; Toshiya Mitomo; Hiroyuki Kobayashi; Hiroshi Yoshida; Hideaki Majima; Ryuichi Fujimoto; Hiroshi Tsurumi (ESSCIRC, 2017)

An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer. - Shusuke Kawai; Hiromitsu Aoyama; Rui Ito; Yutaka Shimizu; Mitsuyuki Ashida; Asuka Maki; Tomohiko Takeuchi; Hiroyuki Kobayashi; Go Urakawa; Hiroaki Hoshino; Shigehito Saigusa; Kazushi Koyama; et al. (ISSCC, 2018)

An 802.11ax 4 × 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer. - Shusuke Kawai; Rui Ito; Kengo Nakata; Yutaka Shimizu; Motoki Nagata; Tomohiko Takeuchi; Hiroyuki Kobayashi; Katsuyuki Ikeuchi; Takayuki Kato; Yosuke Hagiwara; Yuki Fujimura; Kentaro Yoshioka; et al. (IEEE J. Solid State Circuits, 2018)

A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems. - Takashi Toi; Junji Wadatsumi; Hiroyuki Kobayashi; Yutaka Shimizu; Yuji Satoh; Makoto Morimoto; Rui Ito; Mitsuyuki Ashida; Yuta Tsubouchi; Mai Nozawa; Go Urakawa; Jun Deguchi (ISSCC, 2019)

A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems. - Takashi Toi; Junji Wadatsumi; Hiroyuki Kobayashi; Yutaka Shimizu; Yuji Satoh; Makoto Morimoto; Rui Ito; Mitsuyuki Ashida; Yuta Tsubouchi; Mai Nozawa; Go Urakawa; Jun Deguchi; et al. (IEEE J. Solid State Circuits, 2022)