Rui Liu
Orcid: 0000-0003-1642-3473Affiliations:
- Arizona State University, School of Electrical, Computer, and Energy Engineering, Tempe, AZ, USA
According to our database1,
Rui Liu
authored at least 22 papers
between 2015 and 2020.
Collaborative distances:
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Bibliography
2020
Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on Processing-in-Memory Architectures.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors.
IEEE J. Solid State Circuits, 2020
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
2019
A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
MAX<sup>2</sup>: An ReRAM-Based Neural Network Accelerator That Maximizes Data Reuse and Area Utilization.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
Harnessing Intrinsic Noise in Memristor Hopfield Neural Networks for Combinatorial Optimization.
CoRR, 2019
A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on RRAM Based Processing-In-Memory Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Evaluation of Single Event Effects in SRAM and RRAM Based Neuromorphic Computing System for Inference.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
2018
X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point array.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Analyzing inference robustness of RRAM synaptic array in low-precision neural network.
Proceedings of the 47th European Solid-State Device Research Conference, 2017
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017
2016
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
2015
Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Exploiting resistive cross-point array for compact design of physical unclonable function.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015