Exploiting resistive cross-point array for compact design of physical unclonable function. - Pai-Yu Chen; Runchen Fang; Rui Liu 005; Chaitali Chakrabarti; Yu Cao 001; Shimeng Yu (HOST, 2015)

Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design. - Scott Zuloaga; Rui Liu 005; Pai-Yu Chen; Shimeng Yu (ISCAS, 2015)

Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM. - Robert Karam; Rui Liu 005; Pai-Yu Chen; Shimeng Yu; Swarup Bhunia (ACM Great Lakes Symposium on VLSI, 2016)

A highly reliable and tamper-resistant RRAM PUF: Design and experimental validation. - Rui Liu 005; Huaqiang Wu; Yachun Pang; He Qian; Shimeng Yu (HOST, 2016)

Extending 1kb RRAM array from weak PUF to strong PUF by employment of SHA module. - Rui Liu 005; Huaqiang Wu; Yachun Pang; He Qian; Shimeng Yu (AsianHOST, 2017)

Analyzing inference robustness of RRAM synaptic array in low-precision neural network. - Rui Liu 005; Heng-Yuan Lee; Shimeng Yu (ESSDERC, 2017)

Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point array. - Rui Liu 005; Pai-Yu Chen; Shimeng Yu (ISCAS, 2017)

Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network. - Xiaoyu Sun 001; Rui Liu 005; Yi-Ju Chen; Hsiao-Yun Chiu; Wei-Hao Chen; Meng-Fan Chang; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons. - Xiaoyu Sun 001; Xiaochen Peng; Pai-Yu Chen; Rui Liu 005; Jae-sun Seo; Shimeng Yu (ASP-DAC, 2018)

Parallelizing SRAM arrays with customized bit-cell for binary neural networks. - Rui Liu 005; Xiaochen Peng; Xiaoyu Sun 001; Win-San Khwa; Xin Si; Jia-Jing Chen; Jia-Fang Li; Meng-Fan Chang; Shimeng Yu (DAC, 2018)

XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks. - Xiaoyu Sun 001; Shihui Yin; Xiaochen Peng; Rui Liu 005; Jae-sun Seo; Shimeng Yu (DATE, 2018)

A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. - Win-San Khwa; Jia-Jing Chen; Jia-Fang Li; Xin Si; En-Yu Yang; Xiaoyu Sun 001; Rui Liu 005; Pai-Yu Chen; Qiang Li 021; Shimeng Yu; Meng-Fan Chang (ISSCC, 2018)

X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design. - Rui Liu 005; Pai-Yu Chen; Xiaochen Peng; Shimeng Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Evaluation of Single Event Effects in SRAM and RRAM Based Neuromorphic Computing System for Inference. - Zhilu Ye; Rui Liu 005; Hugh J. Barnaby; Shimeng Yu (IRPS, 2019)

Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on RRAM Based Processing-In-Memory Architecture. - Xiaochen Peng; Rui Liu 005; Shimeng Yu (ISCAS, 2019)

A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. - Xin Si; Jia-Jing Chen; Yung-Ning Tu; Wei-Hsing Huang; Jing-Hong Wang; Yen-Cheng Chiu; Wei-Chen Wei; Ssu-Yen Wu; Xiaoyu Sun 001; Rui Liu 005; Shimeng Yu; Ren-Shuo Liu; et al. (ISSCC, 2019)

Harnessing Intrinsic Noise in Memristor Hopfield Neural Networks for Combinatorial Optimization. - Fuxi Cai; Suhas Kumar; Thomas Van Vaerenbergh; Rui Liu 005; Can Li; Shimeng Yu; Qiangfei Xia; J. Joshua Yang; Raymond G. Beausoleil; Wei Lu 003; John Paul Strachan (CoRR, 2019)

MAX2: An ReRAM-Based Neural Network Accelerator That Maximizes Data Reuse and Area Utilization. - Manqing Mao; Xiaochen Peng; Rui Liu 005; Jingtao Li; Shimeng Yu; Chaitali Chakrabarti (IEEE J. Emerg. Sel. Topics Circuits Syst., 2019)

A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors. - Xin Si; Win-San Khwa; Jia-Jing Chen; Jia-Fang Li; Xiaoyu Sun 001; Rui Liu 005; Shimeng Yu; Hiroyuki Yamauchi; Qiang Li 021; Meng-Fan Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

8T XNOR-SRAM based Parallel Compute-in-Memory for Deep Neural Network Accelerator. - Hongwu Jiang; Rui Liu 005; Shimeng Yu (MWSCAS, 2020)

A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. - Xin Si; Rui Liu 005; Shimeng Yu; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Qiang Li 021; Meng-Fan Chang; Jia-Jing Chen; Yung-Ning Tu; Wei-Hsing Huang; Jing-Hong Wang; et al. (IEEE J. Solid State Circuits, 2020)

Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on Processing-in-Memory Architectures. - Xiaochen Peng; Rui Liu 005; Shimeng Yu (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)