An optimum CMOS switched-capacitor antialiasing decimating filter. - Rui Paulo Martins; José E. Franca; Franco Maloberti (IEEE J. Solid State Circuits, 1993)

New impulse sampled IIR switched-capacitor interpolators. - Seng-Pan U.; Rui Paulo Martins; José E. Franca (ICECS, 1996)

A novel half-band SC architecture for efficient analog impulse sampled interpolation. - Seng-Pan U; Rui Paulo Martins; José E. Franca (ICECS, 1998)

Active feedback amplifier approach for microwave filter. - Wai-Wa Choi; Kam-Weng Tam; P. Vitor; Rui Paulo Martins (ICECS, 1999)

New microwave bandstop filter using lumped and transversal network. - Kam-Weng Tam; P. Vitor; J. C. Freire; Rui Paulo Martins (ISCAS (6), 1999)

Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity. - Seng-Pan U.; Rui Paulo Martins; José E. Franca (ISCAS (2), 1999)

High performance multirate SC circuits with predictive correlated double sampling technique. - Seng-Pan U.; Rui Paulo Martins; José E. Franca (ISCAS (2), 1999)

A modular approach for high Q microwave CMOS active inductor design. - Ka Hing Chiang; K. V. Chiang; K. F. Lam; Wai-Wa Choi; Kam-Weng Tam; Rui Paulo Martins (ICECS, 2000)

Interactive SC multirate compiler applied to multistage decimator design. - Cheong Ngai; Rui Paulo Martins (ISCAS, 2000)

A linear-phase halfband SC video interpolation filter with coefficient-sharing and spread-reduction. - Seng-Pan U; Rui Paulo Martins; José E. Franca (ISCAS, 2000)

High-frequency low-power multirate SC realizations for NTSC/PAL digital video filtering. - Seng-Pan U.; Rui Paulo Martins; José E. Franca (ISCAS (1), 2001)

A high-speed frequency up-translated SC bandpass filter with auto-zeroing for DDFS systems. - Seng-Pan U.; Rui Paulo Martins; José E. Franca (ISCAS (1), 2001)

N-path multirate sigma-delta modulator for high-frequency applications. - Fan Lou; Seng-Pan U; Rui Paulo Martins (ICECS, 2002)

Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems. - Seng-Pan U.; Rui Paulo Martins; José E. Franca (ISCAS (4), 2002)

Quantitative noise analysis of jitter-induced nonuniformly sampled-and-held signals. - Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ICASSP (6), 2003)

Frequency-downconversion and IF channel selection A-DQS sample-and-hold pair for two-step-channel-select low-IF receiver. - Pui-In Mak; Chi-sam Sou; Seng-Pan U; Rui Paulo Martins (ICECS, 2003)

A front-to-back-end modeling of I/Q mismatch effects in a complex-IF receiver for image-rejection enhancement. - Pui-In Mak; Seng-Pan U; Rui Paulo Martins (ICECS, 2003)

A 10.7-MHz bandpass sigma-delta modulator using double-delay single-opamp SC resonator with double-sampling. - Chon-In Lao; Ho-leng Leong; Kuoi-Fok Au; Kuok-Hang Mok; Seng-Pan U.; Rui Paulo Martins (ISCAS (1), 2003)

Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output. - Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; José E. Franca (ISCAS (1), 2003)

An I/Q-multiplexed and OTA-shared CMOS pipelined ADC with an A-DQS S/H front-end for two-step-channel-select low-IF receiver. - Pui-In Mak; Kin-Kwan Ma; Weng-leng Mok; Chi-sam Sou; Kit-man Ho; Cheng-Man Ng; Seng-Pan U.; Rui Paulo Martins (ISCAS (1), 2004)

A low-IF/zero-IF reconfigurable receiver with two-step channel selection technique for multistandard applications. - Pui-In Mak; Seng-Pan U.; Rui Paulo Martins (ISCAS (4), 2004)

A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems. - Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS (1), 2004)

Novel interdigital microstrip bandpass filter with improved spurious response. - Sio Weng Ting; Kam-Weng Tam; Rui Paulo Martins (ISCAS (1), 2004)

A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-μ hboxm CMOS. - Seng-Pan U; Rui Paulo Martins; José E. Franca (IEEE J. Solid State Circuits, 2004)

Exact spectra analysis of sampled signals with jitter-induced nonuniformly holding effects. - Seng-Pan U.; Sai-Weng Sin; Rui Paulo Martins (IEEE Trans. Instrum. Meas., 2004)

A 1-V transient-free and DC-offset-canceled PGA with a 17.1-MHz constant bandwidth over 52-dB control range in 0.35-μm CMOS. - Pui-In Mak; Seng-Pan U; Rui Paulo Martins (CICC, 2005)

A robust 3rd order low-distortion multi-bit sigma-delta modulator with reduced number of op-amps for WCDMA. - Kin-Sang Chio; Seng-Pan U.; Rui Paulo Martins (ISCAS (4), 2005)

A novel microstrip bandpass filter design using asymmetric parallel coupled-line. - Si-Weng Fok; Phillip Ngai Cheong; Kam-Weng Tam; Rui Paulo Martins (ISCAS (1), 2005)

A frequency up-conversion and two-step channel selection embedded CMOS D/A interface. - Ka-Hou Ao Ieong; Chong-Yin Fok; Pui-In Mak; Seng-Pan U.; Rui Paulo Martins (ISCAS (1), 2005)

A novel semi-MASH sub-stage for high-order cascade sigma-delta modulators. - Chon-In Lao; Seng-Pan U.; Rui Paulo Martins (ISCAS (4), 2005)

A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuits. - Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS (2), 2005)

A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits. - Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS (2), 2005)

Two-step channel selection-a novel technique for reconfigurable multistandard transceiver front-ends. - Pui-In Mak; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A 1-V 2.5-mW Transient-Improved Current-Steering DAC using Charge-Removal-Replacement Technique. - Ka-Hou Ao Ieong; Seng-Pan U.; Rui Paulo Martins (APCCAS, 2006)

A dual-mode low-distortion sigma-delta modulator with relaxing comparator accuracy. - Kin-Sang Chio; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2006)

A novel effective bandpass semi-MASH sigma-delta modulator with double-sampling mismatch-free resonator. - Chon-In Lao; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2006)

A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications. - Jun-Xia Ma; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2006)

Design and test strategy underlying a low-voltage analog-baseband IC for 802.11a/b/g WLAN SiP receivers. - Pui-In Mak; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2006)

A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits. - Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2006)

A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADC. - Weng-leng Mok; Pui-In Mak; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2007)

Experimental 1-V flexible-IF CMOS analoguebaseband chain for IEEE 802.11a/b/g WLAN receivers. - Pui-In Mak; Seng-Pan U; Rui Paulo Martins (IET Circuits Devices Syst., 2007)

Interactive IIR SC Multirate Compiler Applied to Multistage decimator Design. - Phillip Ngai Cheong; Rui Paulo Martins (J. Circuits Syst. Comput., 2007)

A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs. - U. Fat Chio; He Gong Wei; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo da Silva Martins (APCCAS, 2008)

A pseudo-differential comparator-based pipelined ADC with common mode feedforward technique. - Li Ding; Sio Chan; Kim-Fai Wong; Sai-Weng Sin; Seng-Pan U; Rui Paulo da Silva Martins (APCCAS, 2008)

A novel CMOS switched-current mode sequential shift forward inference circuit for fuzzy logic controller. - Ngai Kong; Seng-Pan U; Rui Paulo Martins (APCCAS, 2008)

A DC-offset-compensated, CT/DT hybrid filter with process-insensitive cutoff and low in-band group-delay variation for WLAN receivers. - Ka-Fai Un; Pui-In Mak; Rui Paulo da Silva Martins (APCCAS, 2008)

A process- and temperature- insensitive current-controlled delay generator for sampled-data systems. - He Gong Wei; U. Fat Chio; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo da Silva Martins (APCCAS, 2008)

A 1-V 90dB DR audio stereo DAC with embedding headphone driver. - Kim-Fai Wong; Ka-Ian Lei; Seng-Pan U; Rui Paulo da Silva Martins (APCCAS, 2008)

A power-efficient capacitor structure for high-speed charge recycling SAR ADCs. - Yan Zhu 001; U. Fat Chio; He Gong Wei; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ICECS, 2008)

An open-source-input, ultra-wideband LNA with mixed-voltage ESD protection for full-band (170-to-1700 MHz) mobile TV tuners. - Pui-In Mak; Ka-Hou Ao Ieong; Rui Paulo Martins (ISCAS, 2008)

A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier. - He Gong Wei; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2008)

On the Design of a Programmable-Gain Amplifier With Built-In Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems. - Pui-In Mak; Seng-Pan U.; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch. - Sai-Weng Sin; U-Fat Chio; Seng-Pan U.; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps. - Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A 90nm CMOS Bio-potential Signal Readout Front-end with Improved Powerline Interference Rejection. - Chon-Teng Ma; Pui-In Mak; Mang I Vai; Peng Un Mak; Sio-Hang Pun; Feng Wan; Rui Paulo Martins (ISCAS, 2009)

An Open-loop Octave-phase Local-oscillator Generator with High-precision Correlated Phases for VHF/UHF Mobile-TV Tuners. - Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (ISCAS, 2009)

Design of an ESD-Protected Ultra-Wideband LNA in Nanoscale CMOS for Full-Band Mobile TV Tuners. - Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs. - Li Ding; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (APCCAS, 2010)

A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators. - Yang Jiang 002; Kim-Fai Wong; Chen-Yan Cai; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (APCCAS, 2010)

An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H. - Sai-Weng Sin; Li Ding; Yan Zhu 001; He Gong Wei; Chi-Hang Chan; U. Fat Chio; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (ESSCIRC, 2010)

A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators. - Yang Jiang 002; Kim-Fai Wong; Chen-Yan Cai; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ICECS, 2010)

An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications. - Guohe Yin; U. Fat Chio; He Gong Wei; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Zhihua Wang 001 (ICECS, 2010)

SC biquad filter with hybrid utilization of OpAmp and comparator-based circuit. - Miguel A. Martins; Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (ISCAS, 2010)

A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs. - Yan Zhu 001; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2010)

1.2-V, 10-bit, 60-360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 μm CMOS with minimised supply headroom. - Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IET Circuits Devices Syst., 2010)

A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS. - Yan Zhu 001; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2010)

Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC. - U-Fat Chio; He Gong Wei; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Analysis and Design of Open-Loop Multiphase Local-Oscillator Generator for Wireless Applications. - Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS. - He Gong Wei; U-Fat Chio; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs. - Yan Zhu 001; U. Fat Chio; He Gong Wei; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (VLSI Design, 2010)

A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation. - Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (A-SSCC, 2011)

A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS. - Chi-Hang Chan; Yan Zhu 001; U. Fat Chio; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2011)

A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators. - Si-Seng Wong; U. Fat Chio; Chi-Hang Chan; Hou-Lon Choi; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2011)

An ultra-low-power filtering technique for biomedical applications. - Tan-Tan Zhang; Pui-In Mak; Mang I Vai; Peng Un Mak; Feng Wan; Rui Paulo Martins (EMBC, 2011)

A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration. - U. Fat Chio; Chi-Hang Chan; Hou-Lon Choi; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ESSCIRC, 2011)

A highly-linear ultra-wideband balun-LNA for cognitive radios. - Weng-Fai Cheng; Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (EUROCON, 2011)

A high-voltage-enabled recycling folded cascode OpAmp for nanoscale CMOS technologies. - Miao Liu; Pui-In Mak; Zushu Yan; Rui Paulo Martins (ISCAS, 2011)

A single-to-differential LNA topology with robust output gain-phase balancing against balun imbalance. - Miguel A. Martins; Pui-In Mak; Rui Paulo Martins (ISCAS, 2011)

Hybrid loopfilter sigma-delta modulator with NTF zero compensation. - Arshad Hussain; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ISOCC, 2011)

A 0.46mm2 4dB-NF unified receiver front-end for full-band mobile TV in 65nm CMOS. - Pui-In Mak; Rui Paulo Martins (ISSCC, 2011)

A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS. - He Gong Wei; Chi-Hang Chan; U-Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (ISSCC, 2011)

A 0.46-mm 2 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS. - Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2011)

A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators. - Yun Du; Tao He; Yang Jiang 002; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (APCCAS, 2012)

A DT 0-2 MASH ΣΔ modulator with VCO-based quantizer for enhanced linearity. - Tao He; Yun Du; Yang Jiang 002; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (APCCAS, 2012)

A dynamic-range-improved 2.4GHz WLAN class-E PA combining PWPM and cascode modulation. - Yinsidi Jiao; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (APCCAS, 2012)

A 10-bit SAR ADC with two redundant decisions and splitted-MSB-cap DAC array. - Wen-Lan Wu; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (APCCAS, 2012)

A 0.8 µW 8-bit 1.5∼20-pF-input-range capacitance-to-digital converter for lab-on-chip digital microfluidics systems. - Yanjie Xiao; Tan-Tan Zhang; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (BioCAS, 2012)

A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC. - Si-Seng Wong; U-Fat Chio; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (CICC, 2012)

A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique. - Rui Wang; U-Fat Chio; Sai-Weng Sin; Seng-Pan U.; Zhihua Wang 001; Rui Paulo Martins (ESSCIRC, 2012)

A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS. - Guohe Yin; He Gong Wei; U-Fat Chio; Sai-Weng Sin; Seng-Pan U.; Zhihua Wang 001; Rui Paulo Martins (ESSCIRC, 2012)

A 10MHz BW 78dB DR CT ΣΔ modulator with novel switched high linearity VCO-based quantizer. - Tao He; Yang Jiang 002; Yun Du; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2012)

A 0.02-to-6GHz SDR balun-LNA using a triple-stage inverter-based amplifier. - Miguel A. Martins; Pui-In Mak; Rui Paulo Martins (ISCAS, 2012)

A 0.016mm2 144μW three-stage amplifier capable of driving 1-to-15nF capacitive load with >0.95MHz GBW. - Zushu Yan; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (ISSCC, 2012)

An ELD tracking compensation technique for active-RC CT ΣΔ modulators. - Chen-Yan Cai; Yang Jiang 002; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (MWSCAS, 2012)

A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC. - Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (VLSIC, 2012)

A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (VLSIC, 2012)

An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC. - He Gong Wei; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2012)

A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation. - Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2012)

A 0.83-µW QRS Detection Processor Using Quadratic Spline Wavelet Transform for Wireless ECG Acquisition in 0.35-µm CMOS. - Chio-In Ieong; Pui-In Mak; Chi-Pang Lam; Cheng Dong; Mang I Vai; Peng Un Mak; Sio-Hang Pun; Feng Wan; Rui Paulo Martins (IEEE Trans. Biomed. Circuits Syst., 2012)

Sub-threshold standard cell library design for ultra-low power biomedical applications. - Mingzhong Li; Chio-In Ieong; Man-Kay Law; Pui-In Mak; Mang I Vai; Rui Paulo Martins (EMBC, 2013)

A 0.5V 10GHz 8-phase LC-VCO Combining current-reuse and back-gate-coupling techniques consuming 2mW. - Md. Tawfiq Amin; Pui-In Mak; Rui Paulo Martins (ISCAS, 2013)

A continuous-time VCO-assisted VCO-based ΣΔ modulator with 76.6dB SNDR and 10MHz BW. - Yun Du; Tao He; Yang Jiang 002; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2013)

A 1.83 μW, 0.78 μVrms input referred noise neural recording front end. - Jiangchao Wu; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (ISCAS, 2013)

A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS. - Wen-Lan Wu; Yan Zhu 001; Li Ding; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2013)

A 1.7mW 0.22mm2 2.4GHz ZigBee RX exploiting a current-reuse blixer + hybrid filter topology in 65nm CMOS. - Zhicheng Lin; Pui-In Mak; Rui Paulo Martins (ISSCC, 2013)

A background gain- calibration technique for low voltage pipelined ADCs based on nonlinear interpolation. - Li Ding; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (MWSCAS, 2013)

A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2013)

A 53-to-75-mW, 59.3-dB HRR, TV-Band White-Space Transmitter Using a Low-Frequency Reference LO in 65-nm CMOS. - Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2013)

A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. - Si-Seng Wong; U-Fat Chio; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE J. Solid State Circuits, 2013)

A 0.016-mm2 144-µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With > 0.95-MHz GBW. - Zushu Yan; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (IEEE J. Solid State Circuits, 2013)

Correction to "A 0.016 mm2 144-µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With >0.95-MHz GBW". - Zushu Yan; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (IEEE J. Solid State Circuits, 2013)

15-nW Biopotential LPFs in 0.35-µm CMOS Using Subthreshold-Source-Follower Biquads With and Without Gain Compensation. - Tan-Tan Zhang; Pui-In Mak; Mang I Vai; Peng Un Mak; Man-Kay Law; Sio-Hang Pun; Feng Wan; Rui Paulo Martins (IEEE Trans. Biomed. Circuits Syst., 2013)

A Nonrecursive Digital Calibration Technique for Joint Elimination of Transmitter and Receiver I/Q Imbalances With Minimized Add-On Hardware. - Wei-Han Yu; Chak-Fong Cheang; Pui-In Mak; Weng-Fai Cheng; Ka-Fai Un; U-Wai Lok; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A 104μW EMI-resisting bandgap voltage reference achieving -20dB PSRR, and 5% DC shift under a 4dBm EMI level. - Shiheng Yang; Pui-In Mak; Rui Paulo Martins (APCCAS, 2014)

Design considerations of a low-noise receiver front-end and its spiral coil for portable NMR screening. - Diyang Zhao; Ka-Meng Lei; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (APCCAS, 2014)

An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC. - Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (ESSCIRC, 2014)

Jitter-resistant Capacitor Based Sine-Shaped DAC for Continuous-Time Sigma-Delta modulators. - Da Feng; Franco Maloberti; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ISCAS, 2014)

Micropower two-stage amplifier employing recycling current-buffer Miller compensation. - Wei Wang 177; Zushu Yan; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (ISCAS, 2014)

A 0.3-V, 37.5-nW 1.5∼6.5-pF-input-range supply voltage tolerant capacitive sensor readout. - Suyan Fan; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (ISIC, 2014)

3.9 An RF-to-BB current-reuse wideband receiver with parallel N-path active/passive mixers and a single-MOS pole-zero LPF. - Fujian Lin; Pui-In Mak; Rui Paulo Martins (ISSCC, 2014)

9.4 A 0.5V 1.15mW 0.2mm2 Sub-GHz ZigBee receiver supporting 433/860/915/960MHz ISM bands with zero external components. - Zhicheng Lin; Pui-In Mak; Rui Paulo Martins (ISSCC, 2014)

17.2 A 0.0013mm2 3.6μW nested-current-mirror single-stage amplifier driving 0.15-to-15nF capacitive loads with >62° phase margin. - Zushu Yan; Pui-In Mak; Man-Kay Law; Rui Paulo Martins; Franco Maloberti (ISSCC, 2014)

Enhancing the performances of recycling folded cascode OpAmp in nanoscale CMOS through voltage supply doubling and design for reliability. - Pui-In Mak; Miao Liu; Yaohua Zhao; Rui Paulo Martins (Int. J. Circuit Theory Appl., 2014)

A 2.4 GHz ZigBee Receiver Exploiting an RF-to-BB-Current-Reuse Blixer + Hybrid Filter Topology in 65 nm CMOS. - Zhicheng Lin; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2014)

An RF-to-BB-Current-Reuse Wideband Receiver With Parallel N-Path Active/Passive Mixers and a Single-MOS Pole-Zero LPF. - Fujian Lin; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2014)

A Sub-GHz Multi-ISM-Band ZigBee Receiver Using Function-Reuse and Gain-Boosted N-Path Techniques for IoT Applications. - Zhicheng Lin; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2014)

Analysis and Modeling of a Gain-Boosted N-Path Switched-Capacitor Bandpass Filter. - Zhicheng Lin; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Split-SAR ADCs: Improved Linearity With Power and Speed Optimization. - Yan Zhu 001; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation. - Jianwei Liu 005; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2015)

26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ISSCC, 2015)

2.4 A 0.028mm2 11mW single-mixing blocker-tolerant receiver with double-RF N-path filtering, S11 centering, +13dBm OB-IIP3 and 1.5-to-2.9dB NF. - Zhicheng Lin; Pui-In Mak; Rui Paulo Martins (ISSCC, 2015)

20.4 A 123-phase DC-DC converter-ring with fast-DVS for microprocessors. - Yan Lu 002; Junmin Jiang; Wing-Hung Ki; C. Patrick Yue; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ISSCC, 2015)

Polyphase Decomposition for Tunable Band-Pass Sigma-Delta A/D Converters. - Da Feng; Franco Maloberti; Sai-Weng Sin; Rui Paulo Martins (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

A 3.6-mW 6-GHz current-reuse VCO-buffer with improved load drivability in 65-nm CMOS. - Md. Tawfiq Amin; Pui-In Mak; Rui Paulo Martins (Int. J. Circuit Theory Appl., 2015)

Corrections to "A 0.02 mm2 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad". - P. V. Ananda Mohan; Yaohua Zhao; Pui-In Mak; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2015)

Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate. - Zushu Yan; Pui-In Mak; Man-Kay Law; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2015)

A 0.02 mm2 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad. - Yaohua Zhao; Pui-In Mak; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2015)

A Combinatorial Impairment-Compensation Digital Predistorter for a Sub-GHz IEEE 802.11af-WLAN CMOS Transmitter Covering a 10x-Wide RF Bandwidth. - Chak-Fong Cheang; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 0.0045-mm2 32.4-µW Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation. - Zushu Yan; Wei Wang 177; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs. - Jianyu Zhong; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Energy Optimized Subthreshold VLSI Logic Family With Unbalanced Pull-Up/Down Network and Inverse Narrow-Width Techniques. - Mingzhong Li; Chio-In Ieong; Man-Kay Law; Pui-In Mak; Mang I Vai; Sio-Hang Pun; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Improving the Linearity and Power Efficiency of Active Switched-Capacitor Filters in a Compact Die Area. - Yaohua Zhao; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A digital LDO with transient enhancement and limit cycle oscillation reduction. - Mo Huang; Yan Lu 002; Seng-Pan U; Rui Paulo Martins (APCCAS, 2016)

Time-domain I/Q-LOFT compensator using a simple envelope detector for a sub-GHz IEEE 802.11af WLAN transmitter. - Chak-Fong Cheang; Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (ASP-DAC, 2016)

Sub-µW QRS detection processor using quadratic spline wavelet transform and maxima modulus pair recognition for power-efficient wireless arrhythmia monitoring. - Chio-In Ieong; Pui-In Mak; Mang I Vai; Rui Paulo Martins (ASP-DAC, 2016)

Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques. - Mingzhong Li; Chio-In Ieong; Man-Kay Law; Pui-In Mak; Mang I Vai; Sio-Hang Pun; Rui Paulo Martins (ASP-DAC, 2016)

A 0.011mm2 60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages. - Chi-Hang Chan; Yan Zhu 001; Iok-Meng Ho; Wai-Hong Zhang; Chon-Lam Lio; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2016)

A high DR multi-channel stage-shared hybrid front-end for integrated power electronics controller. - Yuan Ren; Sai-Weng Sin; Chi-Seng Lam; Man-Chung Wong; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2016)

An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology. - Dante Gabriel Muratore; Alper Akdikmen; Edoardo Bonizzoni; Franco Maloberti; U. Fat Chio; Sai-Weng Sin; Rui Paulo Martins (ESSCIRC, 2016)

A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction. - Jianyu Zhong; Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ESSCIRC, 2016)

A high-Q spiral inductor with dual-layer patterned floating shield in a class-B VCO achieving a 190.5-dBc/Hz FoM. - Chee-Cheow Lim; Harikrishnan Ramiah; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (ISCAS, 2016)

A 94-dB DR, 105-Hz bandwidth interface circuit for inertial navigation applications. - Wei Li; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ISIC, 2016)

28.1 A handheld 50pM-sensitivity micro-NMR CMOS platform with B-field stabilization for multi-type biological/chemical assays. - Ka-Meng Lei; Hadi Heidari; Pui-In Mak; Man-Kay Law; Franco Maloberti; Rui Paulo Martins (ISSCC, 2016)

26.9 A 0.038mm2 SAW-less multiband transceiver using an N-Path SC gain loop. - Gengzhen Qi; Pui-In Mak; Rui Paulo Martins (ISSCC, 2016)

2.7 A 0.003mm2 1.7-to-3.5GHz dual-mode time-interleaved ring-VCO achieving 90-to-150kHz 1/f3 phase-noise corner. - Jun Yin 001; Pui-In Mak; Franco Maloberti; Rui Paulo Martins (ISSCC, 2016)

Wide Input Range Supply Voltage Tolerant Capacitive Sensor Readout Using On-Chip Solar Cell. - Suyan Fan; Man-Kay Law; Mingzhong Li; Zhiyuan Chen 002; Chio-In Ieong; Pui-In Mak; Rui Paulo Martins (J. Circuits Syst. Comput., 2016)

A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE J. Solid State Circuits, 2016)

A µNMR CMOS Transceiver Using a Butterfly-Coil Input for Integration With a Digital Microfluidic Device Inside a Portable Magnet. - Ka-Meng Lei; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (IEEE J. Solid State Circuits, 2016)

A Time-Interleaved Ring-VCO with Reduced 1/f3 Phase Noise Corner, Extended Tuning Range and Inherent Divided Output. - Jun Yin 001; Pui-In Mak; Franco Maloberti; Rui Paulo Martins (IEEE J. Solid State Circuits, 2016)

An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS. - Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (IEEE J. Solid State Circuits, 2016)

A Fully Integrated Digital LDO With Coarse-Fine-Tuning and Burst-Mode Operation. - Mo Huang; Yan Lu 002; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators. - Mo Huang; Yan Lu 002; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins; Wing-Hung Ki (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 2-µW 45-nV/√Hz Readout Front End With Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop. - Jiangchao Wu; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC. - Yan Zhu 001; Chi-Hang Chan; Si-Seng Wong; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC. - Jianwei Liu 005; Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo da Silva Martins (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 5-bit 2 GS/s binary-search ADC with charge-steering comparators. - U. Fat Chio; Sai-Weng Sin; Seng-Pan U; Franco Maloberti; Rui Paulo Martins (A-SSCC, 2017)

A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS. - Wei Wang 177; Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2017)

A missing-code-detection gain error calibration achieving 63dB SNR for an 11-bit ADC. - Guan-Cheng Wang 002; Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (ESSCIRC, 2017)

CCM operation analysis and parameters design of Negative Output Elementary Luo Converter for ripple suppression. - Chi-Wa U; Chi-Seng Lam; Man-Kay Law; Sai-Weng Sin; Man-Chung Wong; Seng-Pan U; Rui Paulo Martins (IECON, 2017)

A 0.4V 4.8μW 16MHz CMOS crystal oscillator achieving 74-fold startup-time reduction using momentary detuning. - Ka-Meng Lei; Pui-In Mak; Rui Paulo Martins (ISCAS, 2017)

Piecewise BJT process spread compensation exploiting base recombination current. - Dapeng Sun; Man-Kay Law; Bo Wang 012; Pui-In Mak; Rui Paulo Martins (ISCAS, 2017)

A digital PWM controlled KY step-up converter based on frequency domain ΣΔ ADC. - Xia Du; Chi-Seng Lam; Sai-Weng Sin; Man-Kay Law; Franco Maloberti; Man-Chung Wong; Seng-Pan U; Rui Paulo Martins (ISIE, 2017)

22.2 A 1.7mm2 inductorless fully integrated flipping-capacitor rectifier (FCR) for piezoelectric energy harvesting with 483% power-extraction enhancement. - Zhiyuan Chen 002; Man-Kay Law; Pui-In Mak; Wing-Hung Ki; Rui Paulo Martins (ISSCC, 2017)

16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration. - Chi-Hang Chan; Yan Zhu 001; Iok-Meng Ho; Wai-Hong Zhang; Seng-Pan U; Rui Paulo Martins (ISSCC, 2017)

20.4 An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control. - Mo Huang; Yan Lu 002; Seng-Pan U; Rui Paulo Martins (ISSCC, 2017)

22.4 A reconfigurable bidirectional wireless power transceiver with maximum-current charging mode and 58.6% battery-to-battery efficiency. - Mo Huang; Yan Lu 002; Seng-Pan U; Rui Paulo Martins (ISSCC, 2017)

20.5 A dual-symmetrical-output switched-capacitor converter with dynamic power cells and minimized cross regulation for application processors in 28nm CMOS. - Junmin Jiang; Yan Lu 002; Wing-Hung Ki; Seng-Pan U; Rui Paulo Martins (ISSCC, 2017)

24.4 A 0.18V 382µW bluetooth low-energy (BLE) receiver with 1.33nW sleep power for energy-harvesting applications in 28nm CMOS. - Wei-Han Yu; Haidong Yi; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (ISSCC, 2017)

60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration. - Chi-Hang Chan; Yan Zhu 001; Cheng Li 010; Wai-Hong Zhang; Iok-Meng Ho; Lai Wei; Seng-Pan U; Rui Paulo Martins (IEEE J. Solid State Circuits, 2017)

Fully Integrated Inductor-Less Flipping-Capacitor Rectifier for Piezoelectric Energy Harvesting. - Zhiyuan Chen 002; Man-Kay Law; Pui-In Mak; Wing-Hung Ki; Rui Paulo Martins (IEEE J. Solid State Circuits, 2017)

A Handheld High-Sensitivity Micro-NMR CMOS Platform With B-Field Stabilization for Multi-Type Biological/Chemical Assays. - Ka-Meng Lei; Hadi Heidari; Pui-In Mak; Man-Kay Law; Franco Maloberti; Rui Paulo Martins (IEEE J. Solid State Circuits, 2017)

A 2.4-GHz ZigBee Transmitter Using a Function-Reuse Class-F DCO-PA and an ADPLL Achieving 22.6% (14.5%) System Efficiency at 6-dBm (0-dBm) Pout. - Xingqiang Peng; Jun Yin 001; Pui-In Mak; Wei-Han Yu; Rui Paulo Martins (IEEE J. Solid State Circuits, 2017)

A 0.038-mm2 SAW-Less Multiband Transceiver Using an N-Path SC Gain Loop. - Gengzhen Qi; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2017)

A sub-1V 78-nA bandgap reference with curvature compensation. - Ziyang Luo; Yan Lu 002; Mo Huang; Junmin Jiang; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (Microelectron. J., 2017)

A Single-Chip Solar Energy Harvesting IC Using Integrated Photodiodes for Biomedical Implant Applications. - Zhiyuan Chen 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Biomed. Circuits Syst., 2017)

Metastablility in SAR ADCs. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Boris Murmann; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting. - Yan Lu 002; Haojuan Dai; Mo Huang; Man-Kay Law; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 73.9%-Efficiency CMOS Rectifier Using a Lower DC Feeding (LDCF) Self-Body-Biasing Technique for Far-Field RF Energy-Harvesting Systems. - Amin Khalili Moghaddam; Joon Huang Chuah; Harikrishnan Ramiah; Jalil Ahmadian; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing. - Liang Qi 002; Sai-Weng Sin; Seng-Pan U; Franco Maloberti; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A High-Voltage-Enabled Class-D Polar PA Using Interactive AM-AM Modulation, Dynamic Matching, and Power-Gating for Average PAE Enhancement. - Wei-Han Yu; Xingqiang Peng; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 12b 180MS/s 0.068mm2 With Full-Calibration-Integrated Pipelined-SAR ADC. - Jianyu Zhong; Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations. - Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications. - Arshad Hussain; Sai-Weng Sin; Chi-Hang Chan; Ben Seng-Pan U; Franco Maloberti; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 0.45 V 147-375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures. - Chio-In Ieong; Mingzhong Li; Man-Kay Law; Pui-In Mak; Mang I Vai; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{ mathrm {cm}}$ -Based Switching. - Dezhi Xing; Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Fan Ye 001; Junyan Ren; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A dual-output SC converter with dynamic power allocation for multicore application processors. - Junmin Jiang; Yan Lu 002; Xun Liu; Wing-Hung Ki; Philip K. T. Mok; Seng-Pan U; Rui Paulo Martins (ASP-DAC, 2018)

An 11b 1GS/s Time-Interleaved ADC with Linearity Enhanced T/H. - Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (A-SSCC, 2018)

A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler. - Wenning Jiang; Yan Zhu 001; Chi-Hang Chan; Boris Murmann; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2018)

A 2.4-GHz Single-Pin Antenna Interface RF Front-End with a Function-Reuse Single-MOS VCO-PA and a Push-Pull LNA. - Kai Xu; Jun Yin 001; Pui-In Mak; Robert Bogdan Staszewski; Rui Paulo Martins (A-SSCC, 2018)

A 39mW 7b 8GS/s 8-way TI ADC with Cross-linearized Input and Bootstrapped Sampling Buffer Front-end. - Chi-Hang Chan; Yan Zhu 001; Zi-Hao Zheng; Rui Paulo Martins (ESSCIRC, 2018)

A Power Quality Indexes Measurement System Platform with Remote Alarm Notification. - Jianyang Deng; Chi-Seng Lam; Man-Chung Wong; Lei Wang 067; Sai-Weng Sin; Rui Paulo Martins (IECON, 2018)

A Dual-Loop Digital LDO Regulator with Asynchronous-Flash Binary Coarse Tuning. - Yuanqing Huang; Yan Lu 002; Franco Maloberti; Rui Paulo Martins (ISCAS, 2018)

A 0.4 V 6.4 μW 3.3 MHz CMOS Bootstrapped Relaxation Oscillator with ±0.71% Frequency Deviation over -30 to 100 °C for Wearable and Sensing Applications. - Ka-Meng Lei; Pui-In Mak; Rui Paulo Martins (ISCAS, 2018)

A Single-Stage Current-Mode Active Rectifier with Accurate Output-Current Regulation for IoT. - Fangyu Mao; Yan Lu 002; Jie Lin; Chenchang Zhan; Seng-Pan U; Rui Paulo Martins (ISCAS, 2018)

Design and Control of An Integrated 3-Level Boost Converter under DCM Operation. - Yiwei Tan; Chi-Seng Lam; Sai-Weng Sin; Man-Chung Wong; Rui Paulo Martins (ISCAS, 2018)

A 0.22-to-2.4V-input fine-grained fully integrated rational buck-boost SC DC-DC converter using algorithmic voltage-feed-in (AVFI) topology achieving 84.1% peak efficiency at 13.2mW/mm2. - Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (ISSCC, 2018)

A regulation-free sub-0.5V 16/24MHz crystal oscillator for energy-harvesting BLE radios with 14.2nJ startup energy and 31.8pW steady-state power. - Ka-Meng Lei; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (ISSCC, 2018)

An inverse-class-F CMOS VCO with intrinsic-high-Q 1st- and 2nd-harmonic resonances for 1/f2-to-1/f3 phase-noise suppression achieving 196.2dBc/Hz FOM. - Chee-Cheow Lim; Jun Yin 001; Pui-In Mak; Harikrishnan Ramiah; Rui Paulo Martins (ISSCC, 2018)

A 0.4V 430nA quiescent current NMOS digital LDO with NAND-based analog-assisted loop in 28nm CMOS. - Xiaofei Ma 004; Yan Lu 002; Rui Paulo Martins; Qiang Li 021 (ISSCC, 2018)

A reconfigurable cross-connected wireless-power transceiver for bidirectional device-to-device charging with 78.1% total efficiency. - Fangyu Mao; Yan Lu 002; Seng-Pan U.; Rui Paulo Martins (ISSCC, 2018)

A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM. - Shiheng Yang; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (ISSCC, 2018)

A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS. - Jun Yin 001; Shiheng Yang; Haidong Yi; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (ISSCC, 2018)

Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications. - Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (SMACD, 2018)

A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation for wireless power transfer systems. - Fangyu Mao; Yan Lu 002; Seng-Pan U; Rui Paulo Martins (VLSI-DAT, 2018)

A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ∑Δ ADC Based on the Pipelined-SAR Structure. - Yan Song; Yan Zhu 001; Chi-Hang Chan; Li Geng; Rui Paulo Martins (VLSI Circuits, 2018)

A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS. - Biao Wang; Sai-Weng Sin; Seng-Pan U; Franco Maloberti; Rui Paulo Martins (VLSI Circuits, 2018)

Review and Selection Strategy for High-Accuracy Modeling of PWM Converters in DCM. - Yu-Jun Mao; Chi-Seng Lam; Sai-Weng Sin; Man-Chung Wong; Rui Paulo Martins (J. Electr. Comput. Eng., 2018)

A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration. - Chi-Hang Chan; Yan Zhu 001; Wai-Hong Zhang; Seng-Pan U; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator. - Mo Huang; Yan Lu 002; Seng-Pan U; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

Algorithmic Voltage-Feed-In Topology for Fully Integrated Fine-Grained Rational Buck-Boost Switched-Capacitor DC-DC Converters. - Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

A Regulation-Free Sub-0.5-V 16-/24-MHz Crystal Oscillator With 14.2-nJ Startup Energy and 31.8-µW Steady-State Power. - Ka-Meng Lei; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

An Inverse-Class-F CMOS Oscillator With Intrinsic-High-Q First Harmonic and Second Harmonic Resonances. - Chee-Cheow Lim; Harikrishnan Ramiah; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

Low-Phase-Noise Wideband Mode-Switching Quad-Core-Coupled mm-wave VCO Using a Single-Center-Tapped Switched Inductor. - Yatao Peng; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

A SAW-Less Tunable RF Front End for FDD and IBFD Combining an Electrical-Balance Duplexer and a Switched-LC N-Path LNA. - Gengzhen Qi; Barend van Liempd; Pui-In Mak; Rui Paulo Martins; Jan Craninckx (IEEE J. Solid State Circuits, 2018)

A 5.35-mW 10-MHz Single-Opamp Third-Order CT ΔΣ Modulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS. - Wei Wang 177; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

A 0.18-V 382-µW Bluetooth Low-Energy Receiver Front-End With 1.33-nW Sleep Power for Energy-Harvesting Applications in 28-nm CMOS. - Haidong Yi; Wei-Han Yu; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

Quick and cost-efficient A/D converter static characterization using low-precision testing signal. - Wei Wei Qin; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (Microelectron. J., 2018)

A Hardware-Efficient Feedback Polynomial Topology for DPD Linearization of Power Amplifiers: Theory and FPGA Validation. - Chak-Fong Cheang; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers With Maximized Timing Margin. - Yong Chen 005; Pui-In Mak; Chirn Chye Boon; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 10-MHz Bandwidth Two-Path Third-Order ΣΔ Modulator With Cross-Coupling Branches. - Da Feng; Edoardo Bonizzoni; Franco Maloberti; Sai-Weng Sin; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Nano-Ampere Low-Dropout Regulator Designs for IoT Devices. - Yuanqing Huang; Yan Lu 002; Franco Maloberti; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Wideband Inductorless dB-Linear Automatic Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications. - Lingshan Kong; Yong Chen 005; Chirn Chye Boon; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current. - Jiaji Mao; Mingqiang Guo; Sai-Weng Sin; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Coin-Battery-Powered LDO-Free 2.4-GHz Bluetooth Low-Energy Transmitter With 34.7% Peak System Efficiency. - Xingqiang Peng; Jun Yin 001; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC. - Guan-Cheng Wang 002; Cheng Li 010; Yan Zhu 001; Jianyu Zhong; Yan Lu 002; Chi-Hang Chan; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Reconfigurable and Extendable Digital Architecture for Mixed Signal Power Electronics Controller. - Ya-Jie Wu; Chi-Seng Lam; Man-Chung Wong; Sai-Weng Sin; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology. - Xiaofeng Yang 004; Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 0.032-mm2 0.15-V Three-Stage Charge-Pump Scheme Using a Differential Bootstrapped Ring-VCO for Energy-Harvesting Applications. - Haidong Yi; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 0.7-2.5 GHz, 61% EIRP System Efficiency, Four-Element MIMO TX System Exploiting Integrated Power-Relaxed Power Amplifiers and an Analog Spatial De-Interleaver. - Wei-Han Yu; Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 220-MHz Bondwire-Based Fully-Integrated KY Converter With Fast Transient Response Under DCM Operation. - Wen-Liang Zeng; Chi-Seng Lam; Sai-Weng Sin; Franco Maloberti; Man-Chung Wong; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 0.19 mm2 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS. - Yan Zhu 001; Chi-Hang Chan; Zi-Hao Zheng; Cheng Li 010; Jianyu Zhong; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Passive Noise Shaping in SAR ADC With Improved Efficiency. - Yan Song; Chi-Hang Chan; Yan Zhu 001; Li Geng; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area. - Guan-Cheng Wang 002; Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique. - Lingshan Kong; Yong Chen 005; Haohong Yu; Quan Pan 002; Chirn Chye Boon; Pui-In Mak; Rui Paulo Martins (APCCAS, 2019)

A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS. - Xiaoteng Zhao; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (APCCAS, 2019)

Multibit Sturdy MASH ΔΣ Modulator with Error-shaped Segmented DACs for Wideband Low-power Applications. - Liang Qi 002; Sai-Weng Sin; Rui Paulo Martins (ASICON, 2019)

A 200-MHz Wide Input Range CMOS Passive Rectifier with Active Bias Tunning. - Xiaofei Li; Fangyu Mao; Pyungwoo Yeon; Yan Lu 002; Maysam Ghovanloo; Rui Paulo Martins (A-SSCC, 2019)

A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta Modulator. - Junhao Liang; Sai-Weng Sin; Seng-Pan U; Franco Maloberti; Rui Paulo Martins; Hanjun Jiang (A-SSCC, 2019)

A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS. - Biao Wang; Sai-Weng Sin; Seng-Pan U; Franco Maloberti; Rui Paulo Martins (A-SSCC, 2019)

A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS. - Zunsong Yang; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (A-SSCC, 2019)

A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration. - Mingqiang Guo; Jiaji Mao; Sai-Weng Sin; He Gong Wei; Rui Paulo Martins (CICC, 2019)

Input Correlated Swap-Sampling Technique for Input Driver Power Reduction in a 12b 25MS/s SAR ADC. - Lai Wei; Xiang-Hui Pan; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (ISCAS, 2019)

A Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier and Capacitor Reuse Multiple-VCR SC DC-DC Achieving 9.3× Energy-Extraction Improvement. - Zhiyuan Chen 002; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Xiaoyang Zeng; Rui Paulo Martins (ISSCC, 2019)

A -246dB Jitter-FoM 2.4GHz Calibration-Free Ring-Oscillator PLL Achieving 9% Jitter Variation Over PVT. - Xiaofeng Yang 004; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (ISSCC, 2019)

A 0.08mm2 25.5-to-29.9GHz Multi-Resonant-RLCM-Tank VCO Using a Single-Turn Multi-Tap Inductor and CM-Only Capacitors Achieving 191.6dBc/Hz FoM and 130kHz 1/f3 PN Corner. - Hao Guo; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (ISSCC, 2019)

A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier. - Wenning Jiang; Yan Zhu 001; Minglei Zhang; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2019)

A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS. - Liang Qi 002; Ankesh Jain; Dongyang Jiang; Sai-Weng Sin; Rui Paulo Martins; Maurits Ortmanns (ISSCC, 2019)

A 72.6dB-SNDR 100MHz-BW 16.36mW CTDSM with Preliminary Sampling and Quantization Scheme in Backend Subranging QTZ. - Wei Wang 177; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (ISSCC, 2019)

A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur. - Zunsong Yang; Yong Chen 005; Shiheng Yang; Pui-In Mak; Rui Paulo Martins (ISSCC, 2019)

A 0.6V 13b 20MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques. - Minglei Zhang; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (ISSCC, 2019)

Using EDA Tools to Push the Performance Boundaries of an Ultralow-Power IoT-VCO at 65nm. - Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (SMACD, 2019)

A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing. - Mingqiang Guo; Jiaji Mao; Sai-Weng Sin; He Gong Wei; Rui Paulo Martins (VLSI Circuits, 2019)

A coin-battery-powered LDO-Free 2.4-GHz Bluetooth Low Energy/ZigBee receiver consuming 2 mA. - Zechariah Balan; Harikrishnan Ramiah; Jagadheswaran Rajendran; Nandini Vitee; Pravinah Nair Shasidharan; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (Integr., 2019)

An Integrated DC-DC Converter With Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery. - U-Fat Chio; Kuo-Chih Wen; Sai-Weng Sin; Chi-Seng Lam; Yan Lu 002; Franco Maloberti; Rui Paulo Martins (IEEE J. Solid State Circuits, 2019)

Algebraic Series-Parallel-Based Switched-Capacitor DC-DC Boost Converter With Wide Input Voltage Range and Enhanced Power Density. - Yang Jiang 002; Man-Kay Law; Zhiyuan Chen 002; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2019)

A Reconfigurable Cross-Connected Wireless-Power Transceiver for Bidirectional Device-to-Device Wireless Charging. - Fangyu Mao; Yan Lu 002; Rui Paulo Martins (IEEE J. Solid State Circuits, 2019)

A 550- $ mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $ Sigma Delta$ ADC With 256 Clock Cycles in 65-nm CMOS. - Biao Wang; Sai-Weng Sin; Seng-Pan U; Franco Maloberti; Rui Paulo Martins (IEEE J. Solid State Circuits, 2019)

A 0.0056-mm2 -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs. - Shiheng Yang; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2019)

A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS. - Shiheng Yang; Jun Yin 001; Haidong Yi; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2019)

A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC With PVT Tracking and Speed-Enhanced Techniques. - Minglei Zhang; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (IEEE J. Solid State Circuits, 2019)

A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis. - Yong Chen 005; Pui-In Mak; Zunsong Yang; Chirn Chye Boon; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

CMOS Cross-Coupled Differential-Drive Rectifier in Subthreshold Operation for Ambient RF Energy Harvesting - Model and Analysis. - Gabriel Chong; Harikrishnan Ramiah; Jun Yin 001; Jagadheswaran Rajendran; Wei Ru Wong; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS. - Chao Fan; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM. - Tongquan Jiang; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 4-b 7-µW Phase Domain ADC With Time Domain Reference Generation for Low-Power FSK/PSK Demodulation. - Xuewei Lei; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC. - Cheng Li 010; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Background Offset Calibration for Comparator Based on Temperature Drift Profile. - Xiaochao Li; Chi-Hang Chan; Qi Zhang 031; Yan Zhu 001; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 5.1-to-7.3 mW, 2.4-to-5 GHz Class-C Mode-Switching Single-Ended-Complementary VCO Achieving >190 dBc/Hz FoM. - Chee-Cheow Lim; Harikrishnan Ramiah; Jun Yin 001; Narendra Kumar 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Comparative Study of 8-Phase Feedforward-Coupling Ring VCOs. - Iat-Fai Sun; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-µs Settling Time for Multi-ISM-Band ULP Radios. - Ka-Fai Un; Gengzhen Qi; Jun Yin 001; Shiheng Yang; Shupeng Yu; Chio-In Ieong; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Fully Integrated High Voltage Pulse Driver Using Switched-Capacitor Voltage Multiplier and Synchronous Charge Compensation in 65-nm CMOS. - Jiangchao Wu; Ka-Chon Lei; Hou-Man Leong; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With Optimal Code Transfer Technique. - Dezhi Xing; Yan Zhu 001; Chi-Hang Chan; Franco Maloberti; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 0.044-mm2 0.5-to-7-GHz Resistor-Plus-Source-Follower-Feedback Noise-Cancelling LNA Achieving a Flat NF of 3.3±0.45 dB. - Haohong Yu; Yong Chen 005; Chirn Chye Boon; Chenyang Li 008; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Design of KY Converter With Constant On-Time Control Under DCM Operation. - Wen-Liang Zeng; Zi-Yang Lin; Chi-Seng Lam; Man-Kay Law; Sai-Weng Sin; Franco Maloberti; Man-Chung Wong; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 0.0018-mm2 153% Locking-Range CML-Based Divider-by-2 With Tunable Self-Resonant Frequency Using an Auxiliary Negative-gm Cell. - Xiaoteng Zhao; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter. - Xinyi Ge; Yong Chen 005; Xiaoteng Zhao; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector. - Jianwei Liu 005; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications. - Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A Single-Stage Delay-Tuned Active Rectifier for Constant-Current Constant-Voltage Wireless Charging. - Xianglong Bai; Fangyu Mao; Yan Lu 002; Chenchang Zhan; Rui Paulo Martins (APCCAS, 2020)

A Power-Efficient Hybrid Single-Inductor Bipolar-Output DC-DC Converter with Floating Negative Output for AMOLED Displays. - Fangyu Mao; Yan Lu 002; Edoardo Bonizzoni; Filippo Boera; Mo Huang; Franco Maloberti; Rui Paulo Martins (CICC, 2020)

A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS. - Xiaoteng Zhao; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (CICC, 2020)

A 10MHz Buck Converter with Type-III Control and Transient Enhancement Transistor. - Shuangxing Zhao; Yan Lu 002; Chenchang Zhan; Rui Paulo Martins (ICTA, 2020)

A Unity-Power-Factor Inductive Power Transfer Converter with Inherent CC-to-CV Transition Ability for Automated Guided Vehicle Charging. - Io-Wa Iam; Iok-U Hoi; Zhicong Huang; Chi-Seng Lam; Pui-In Mak; Rui Paulo Martins (IECON, 2020)

Low Complexity Illumination-Invariant Motion Vector Detection Based on Logarithmic Edge Detection and Edge Difference. - Chuanqi Wei; Jiangchao Wu; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (ISCAS, 2020)

An N × N Multiplier-Based Multi-Bit Strong PUF using Path Delay Extraction. - Chongyao Xu; Jieyun Zhang; Man-Kay Law; Xiaojin Zhao; Pui-In Mak; Rui Paulo Martins (ISCAS, 2020)

A 6.4pJ/Bit Strong Physical Unclonable Function Based on Multiple-Stage Amplifier Chain. - Jieyun Zhang; Xiaojin Zhao; Man-Kay Law; Chongyao Xu; Jiahao Liu; Pui-In Mak; Rui Paulo Martins (ISCAS, 2020)

17.9 A 9mW 54.9-to-63.5GHz Current-Reuse LO Generator with a 186.7dBc/Hz FoM by Unifying a 20GHz 3rd-Harmonic-Rich Current-Output VCO, a Harmonic-Current Filter and a 60GHz TIA. - Chao Fan; Jun Yin 001; Chee-Cheow Lim; Pui-In Mak; Rui Paulo Martins (ISSCC, 2020)

11.5 A 2-Phase Soft-Charging Hybrid Boost Converter with Doubled-Switching Pulse Width and Shared Bootstrap Capacitor Achieving 93.5% Efficiency at a Conversion Ratio of 4.5. - Mo Huang; Yan Lu 002; Rui Paulo Martins (ISSCC, 2020)

10.1 A 1.4-to-2.7GHz FDD SAW-Less Transmitter for 5G-NR Using a BW-Extended N-Path Filter-Modulator, an Isolated-BB Input and a Wideband TIA-Based PA Driver Achieving <-157.5dBc/Hz OB Noise. - Gengzhen Qi; Haijun Shao; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (ISSCC, 2020)

9.6 A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial-Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration. - Yan Song; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2020)

16.2 A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input. - Minglei Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2020)

16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation. - Zihao Zheng; Lai Wei; Jorge Lagos 001; Ewout Martens; Yan Zhu 001; Chi-Hang Chan; Jan Craninckx; Rui Paulo Martins (ISSCC, 2020)

A 0.024-mm2 45.4-GHz-Bandwidth Unity-Gain Output Driver with SDD22<-10dB up to 35 GHz. - Yong Chen 005; Pui-In Mak; Chirn Chye Boon; Rui Paulo Martins (MWSCAS, 2020)

A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS. - Dongyang Jiang; Liang Qi 002; Sai-Weng Sin; Franco Maloberti; Rui Paulo Martins (VLSI Circuits, 2020)

A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SAB-ELD-Merged Integrator and 3-Stage Opamp. - Kai Xing; Wei Wang 177; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (VLSI Circuits, 2020)

A 5 GS/s 29 mW Interleaved SAR ADC With 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications. - Mingqiang Guo; Jiaji Mao; Sai-Weng Sin; He Gong Wei; Rui Paulo Martins (IEEE Access, 2020)

A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector. - Zunsong Yang; Yong Chen 005; Shiheng Yang; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2020)

Analysis, Design and Control of an Integrated Three-Level Buck Converter under DCM Operation. - Wen-Ming Zheng; Wen-Liang Zeng; Chi-Wa U; Chi-Seng Lam; Yan Lu 002; Sai-Weng Sin; Man-Chung Wong; Rui Paulo Martins (J. Circuits Syst. Comput., 2020)

Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier With Capacitor Reuse for Input Power Adaptation. - Zhiyuan Chen 002; Man-Kay Law; Pui-In Mak; Xiaoyang Zeng; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration. - Mingqiang Guo; Jiaji Mao; Sai-Weng Sin; He Gong Wei; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

An Analog-Proportional Digital-Integral Multiloop Digital LDO With PSR Improvement and LCO Reduction. - Mo Huang; Yan Lu 002; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier. - Wenning Jiang; Yan Zhu 001; Minglei Zhang; Chi-Hang Chan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

A VHF Wide-Input Range CMOS Passive Rectifier With Active Bias Tuning. - Xiaofei Li; Fangyu Mao; Yan Lu 002; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance. - Liang Qi 002; Ankesh Jain; Dongyang Jiang; Sai-Weng Sin; Rui Paulo Martins; Maurits Ortmanns (IEEE J. Solid State Circuits, 2020)

A Multiband FDD SAW-Less Transmitter for 5G-NR Featuring a BW-Extended N-Path Filter-Modulator, a Switched-BB Input, and a Wideband TIA-Based PA Driver. - Gengzhen Qi; Haijun Shao; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC. - Yan Song; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization. - Wei Wang 177; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

A Single-Pin Antenna Interface RF Front End Using a Single-MOS DCO-PA and a Push-Pull LNA. - Kai Xu; Jun Yin 001; Pui-In Mak; Robert Bogdan Staszewski; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC With <1.5-ps Uncalibrated Quantization Steps. - Minglei Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

A switched-capacitor power converter with unequal duty cycle for ripple reduction and efficiency improvement. - Yulun Wu; Yerzhan Mustafa; Yan Lu 002; Alex Ruderman; Rui Paulo Martins (Microelectron. J., 2020)

A 3.3-mW 25.2-to-29.4-GHz Current-Reuse VCO Using a Single-Turn Multi-Tap Inductor and Differential-Only Switched-Capacitor Arrays With a 187.6-dBc/Hz FOM. - Yunbo Huang; Yong Chen 005; Hao Guo; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

A 2.4-GHz Mid-Field CMOS Wireless Power Receiver Achieving 46% Maximum PCE and 163-mW Output Power. - Xiaofei Li; Yan Lu 002; Mo Huang; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Digital Battery Management Unit With Built-In Resistance Compensation, Modulated Frequency Detection and Multi-Mode Protection for Fast, Efficient and Safe Charging. - Ji-Xuan Li; Sai-Weng Sin; U. Fat Chio; Ya-Jie Wu; Chi-Seng Lam; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

A 0.04% BER Strong PUF With Cell-Bias-Based CRPs Filtering and Background Offset Calibration. - Jiahao Liu; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

An NMOS Digital LDO With NAND-Based Analog-Assisted Loop in 28-nm CMOS. - Xiaofei Ma 004; Yan Lu 002; Qiang Li 021; Wing-Hung Ki; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools. - Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta; Shenke Zhong; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

A 0.5-V Supply, 36 nW Bandgap Reference With 42 ppm/°C Average Temperature Coefficient Within -40 °C to 120 °C. - Chi-Wa U; Wen-Liang Zeng; Man-Kay Law; Chi-Seng Lam; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

Design Considerations of the Interpolative Digital Transmitter for Quantization Noise and Replicas Rejection. - Ka-Fai Un; Feifei Zhang; Pui-In Mak; Rui Paulo Martins; Anding Zhu; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

LDO-Free Power Management System: A 10-bit Pipelined ADC Directly Powered by Inductor-Based Boost Converter With Ripple Calibration. - Hanyu Wang; Sai-Weng Sin; Chi-Seng Lam; Franco Maloberti; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

A Calibration-Free Ring-Oscillator PLL With Gain Tracking Achieving 9% Jitter Variation Over PVT. - Xiaofeng Yang 004; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

A SAR-ADC-Assisted DC-DC Buck Converter With Fast Transient Recovery. - Wen-Liang Zeng; Edoardo Bonizzoni; Chi-Wa U; Chi-Seng Lam; Sai-Weng Sin; U. Fat Chio; Franco Maloberti; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 470-nA Quiescent Current and 92.7%/94.7% Efficiency DCT/PWM Control Buck Converter With Seamless Mode Selection for IoT Application. - Wen-Liang Zeng; Yuan Ren; Chi-Seng Lam; Sai-Weng Sin; Weng-Keong Che; Ran Ding; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

Cost-Effective Compensation Design for Output Customization and Efficiency Optimization in Series/Series-Parallel Inductive Power Transfer Converter. - Zhicong Huang; Zhijian Fang; Chi-Seng Lam; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Ind. Electron., 2020)

A 3.15-mW +16.0-dBm IIP3 22-dB CG Inductively Source Degenerated Balun-LNA Mixer With Integrated Transformer-Based Gate Inductor and IM2 Injection Technique. - Nandini Vitee; Harikrishnan Ramiah; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 1-V 4-mW Differential-Folded Mixer With Common-Gate Transconductor Using Multiple Feedback Achieving 18.4-dB Conversion Gain, +12.5-dBm IIP3, and 8.5-dB NF. - Nandini Vitee; Harikrishnan Ramiah; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Design of Diode-Connected and Cross-Connected CMOS Rectifiers with Adaptive Tuning for RF Energy Harvesting. - Xiaofei Li; Yan Lu 002; Rui Paulo Martins (APCCAS, 2021)

An Arithmetic Progression Switched-Capacitor DC-DC Converter with Soft VCR Transitions Achieving 93.7% Peak Efficiency and 400 mA Output Current. - Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (A-SSCC, 2021)

A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancement. - Jixuan Li; Jiabao Chen; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (A-SSCC, 2021)

A 0.46pJ/bit Ultralow-Power Entropy-Preselection-Based Strong PUF with Worst-Case BER-6. - Jiahao Liu; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (A-SSCC, 2021)

A 15.2-to-18.2GHz Balanced Dual-Core Inverse-Class-F VCO with Q-Enhanced 2nd-Harmonic Resonance Achieving 187-to-188.1dBc/Hz FoM in 28nm CMOS. - Xi Meng; Junqi Guo; Haoran Li; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (A-SSCC, 2021)

Auto-Calibration Technique for Current-Based Bandgap Voltage Reference. - Chi-Wa U; Man-Kay Law; Chi-Seng Lam; Rui Paulo Martins (A-SSCC, 2021)

Modeling Attack Resistant Strong PUF Exploiting Obfuscated Interconnections With <0.83% Bit-Error Rate. - Chongyao Xu; Jieyun Zhang; Man-Kay Law; Yang Jiang 002; Xiaojin Zhao; Pui-In Mak; Rui Paulo Martins (A-SSCC, 2021)

A 95% Peak Efficiency Modified KY (Boost) Converter for IoT with Continuous Flying Capacitor Charging in DCM. - Wen-Liang Zeng; Caolei Pan; Chi-Seng Lam; Sai-Weng Sin; Chenchang Zhan; Rui Paulo Martins (A-SSCC, 2021)

A Dual-Loop 4-Phase Switching LDO with Scalable Load Capability and Tunable Active Voltage Positioning for Microprocessors. - Xiangyu Mao; Yan Lu 002; Rui Paulo Martins (CICC, 2021)

A 79.1dB-SNDR 20MHz-BW 2nd-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture. - Yanbo Zhang; Jin Zhang 034; Shubin Liu; Zhangming Zhu; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (CICC, 2021)

A Periodically Time-Varying Inductor Applied to The Class-D VCO for Phase Noise Improvement. - Jun Yin 001; Pui-In Mak; Rui Paulo Martins (ESSCIRC, 2021)

A 0.45-V 3.3-µW Resistor-Based Temperature Sensor Achieving 10mK Resolution in 65-nm CMOS. - Ka-Meng Lei; Pui-In Mak; Rui Paulo Martins (ICTA, 2021)

A 3.52-GHz Harmonic-Rich-Shaping VCO with Noise Suppression and Circulation, Achieving -151-dBc/Hz Phase Noise at 10-MHz Offset. - Yunbo Huang; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (ISCAS, 2021)

Discrete-Time MASH Delta-Sigma Modulator with Second-Order Digital Noise Coupling for Wideband High-Resolution Applications. - Xinyu Qin; Jingying Zhang; Liang Qi 002; Sai-Weng Sin; Rui Paulo Martins; Guoxing Wang (ISCAS, 2021)

Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCs. - Mingqiang Guo; Sai-Weng Sin; Rui Paulo Martins (ISOCC, 2021)

A 5.0-to-6.36GHz Wideband-Harmonic-Shaping VCO Achieving 196.9dBc/Hz Peak FoM and 90-to-180kHz 1/f3 PN Corner Without Harmonic Tuning. - Hao Guo; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (ISSCC, 2021)

27.6 A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Background Offset Calibration. - Hongshuai Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2021)

A 4-bit Mixed-Signal MAC Array with Swing Enhancement and Local Kernel Memory. - Wei-Han Yu; Massimo Giordano; Rohan Doshi; Minglei Zhang; Pui-In Mak; Rui Paulo Martins; Boris Murmann (MWSCAS, 2021)

An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC. - Lai Wei; Zihao Zheng; Nereo Markulic; Jorge Lagos 001; Ewout Martens; Yan Zhu 001; Chi-Hang Chan; Jan Craninckx; Rui Paulo Martins (VLSI Circuits, 2021)

A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration. - Minglei Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (VLSI Circuits, 2021)

Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique. - Lingshan Kong; Yong Chen 005; Haohong Yu; Chirn Chye Boon; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2021)

A multi-path switched-capacitor-inductor hybrid DC-DC converter with reduced inductor loss and extended voltage conversion range. - Qiaobo Ma; Xiongjie Zhang; Yang Jiang 002; Katsuhiro Hata; Makoto Takamiya; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (IEICE Electron. Express, 2021)

A 12V-to-1V switched-capacitor-assisted hybrid converter with dual-path charge conduction and zero-voltage switching. - Xiongjie Zhang; Qiaobo Ma; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (IEICE Electron. Express, 2021)

Bird's-eye view of analog and mixed-signal chips for the 21st century. - Rui Paulo Martins; Pui-In Mak; Chi-Hang Chan; Jun Yin 001; Yan Zhu 001; Yong Chen 005; Yan Lu 002; Man-Kay Law; Sai-Weng Sin (Int. J. Circuit Theory Appl., 2021)

A Hybrid Boost Converter With Cross-Connected Flying Capacitors. - Mo Huang; Yan Lu 002; Tingxu Hu; Rui Paulo da Silva Martins (IEEE J. Solid State Circuits, 2021)

A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation. - Dongyang Jiang; Liang Qi 002; Sai-Weng Sin; Franco Maloberti; Rui Paulo Martins (IEEE J. Solid State Circuits, 2021)

A 0.35-V 5, 200-μm2 2.1-MHz Temperature-Resilient Relaxation Oscillator With 667 fJ/Cycle Energy Efficiency Using an Asymmetric Swing-Boosted RC Network and a Dual-Path Comparator. - Ka-Meng Lei; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2021)

A Single-Stage Dual-Output Regulating Rectifier With Hysteretic Current-Wave Modulation. - Jie Lin; Yan Lu 002; Chenchang Zhan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2021)

A Hybrid Single-Inductor Bipolar-Output DC-DC Converter With Floating Negative Output for AMOLED Displays. - Fangyu Mao; Yan Lu 002; Edoardo Bonizzoni; Filippo Boera; Mo Huang; Franco Maloberti; Rui Paulo Martins (IEEE J. Solid State Circuits, 2021)

A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC. - Yan Song; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2021)

A High-Efficiency Dual-Antenna RF Energy Harvesting System Using Full-Energy Extraction With Improved Input Power Response. - Zhaobo Zhang; Chenchang Zhan; Man-Kay Law; Yang Jiang 002; Pui-In Mak; Rui Paulo Martins (IEEE Open J. Circuits Syst., 2021)

A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler. - Wenning Jiang; Yan Zhu 001; Chi-Hang Chan; Boris Murmann; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 3-Phase Resonant Switched-Capacitor Converter for Data Center 48-V Rack Power Distribution. - Chuang Wang 004; Yan Lu 002; Nan Sun 001; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS. - Zunsong Yang; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS. - Xiaoteng Zhao; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A Wide-PCE-Dynamic-Range CMOS Cross-Coupled Differential-Drive Rectifier for Ambient RF Energy Harvesting. - Gabriel Chong; Harikrishnan Ramiah; Jun Yin 001; Jagadheswaran Rajendran; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 3.36-GHz Locking-Tuned Type-I Sampling PLL With -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques. - Yunbo Huang; Yong Chen 005; Hailong Jiao; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Review of Analog-Assisted-Digital and Digital-Assisted-Analog Low Dropout Regulators. - Mo Huang; Yan Lu 002; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Startup Time and Energy-Reduction Techniques for Crystal Oscillators in the IoT Era. - Ka-Meng Lei; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications. - Jixuan Li; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 1.7-to-2.7GHz 35-38% PAE Multiband CMOS Power Amplifier Employing a Digitally-Assisted Analog Pre-Distorter (DAAPD) Reconfigurable Linearization Technique. - Selvakumar Mariappan; Jagadheswaran Rajendran; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

An 800 MHz-to-3.3 GHz 20-MHz Channel Bandwidth WPD CMOS Power Amplifier For Multiband Uplink Radio Transceivers. - Selvakumar Mariappan; Jagadheswaran Rajendran; Harikrishnan Ramiah; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Adaptive Maximum Power Point Tracking With Model-Based Negative Feedback Control and Improved V-f Model. - Yuanfei Wang; Mo Huang; Ping Luo 005; Yan Lu 002; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Highly Integrated 3-Phase 4: 1 Resonant Switched-Capacitor Converter With Parasitic Loss Reduction and Fast Pre-Charge Startup. - Chuang Wang 004; Yan Lu 002; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS. - Shiheng Yang; Jun Yin 001; Tailong Xu; Taimo Yi; Pui-In Mak; Qiang Li 021; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Fully Integrated 10-V Pulse Driver Using Multiband Pulse-Frequency Modulation in 65-nm CMOS. - Jiangchao Wu; Hou-Man Leong; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Design and Implementation of a Low Power Switched-Capacitor-Based Analog Feature Extractor for Voice Keyword Spotting. - Feifei Chen; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (APCCAS, 2022)

High Linearity BJT-Based Time-Domain CMOS Temperature Sensor. - Yu Lei; Qishen Fang; Jiangchao Wu; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (APCCAS, 2022)

Adaptive Line-Transient Enhancement Techniques for Dual-Path Hybrid Converter Achieving Ultra-Low Output Overshoot/Undershoot. - Huihua Li; Qiaobo Ma; Xuchu Mu; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (APCCAS, 2022)

LSB-Reused Protection Technique in Secure SAR ADC against Power Side-Channel Attack. - Lele Fang; Jiahao Liu; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (AsianHOST, 2022)

A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing. - Mingqiang Guo; Sai-Weng Sin; Liang Qi 002; Gang Xiao 001; Rui Paulo Martins (CICC, 2022)

All Rivers Flow to the Sea: A High Power Density Wireless Power Receiver with Split-Dual-Path Rectification and Hybrid-Quad-Path Step-Down Conversion. - Zixiao Lin; Yan Lu 002; Fangyu Mao; Chuang Wang 004; Rui Paulo Martins (CICC, 2022)

A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme. - Lin Wang 115; Yong Chen 005; Chaowei Yang; Xiaoteng Zhao; Pui-In Mak; Franco Maloberti; Rui Paulo Martins (ICECS 2022, 2022)

A Switched-Capacitor Hybrid Quadratic Buck Converter for 48V-Input Wide-Range Conversion. - Ruijie Zhao 003; Xiongjie Zhang; Xuchu Mu; Huihua Li; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (ICECS 2022, 2022)

A Hybrid Boost Converter with Regulated Flying Capacitor Voltage and Reduced Inductor Current for LED Lighting. - Chuang Wang 004; Zixiao Lin; Yan Lu 002; Xiuping Li; Rui Paulo Martins (ISCAS, 2022)

A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC. - Ke Li; Sai-Weng Sin; Liang Qi 002; Weibing Zhao; Guoxing Wang; Rui Paulo Martins (ISCAS, 2022)

An Auxiliary-Loop-Enhanced Fast-Transient FVF LDO as Reference Buffer of a SAR ADC. - Yi Zeng; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (ISCAS, 2022)

A Battery-Input Sub-1V Output 92.9% Peak Efficiency 0.3A/mm2 Current Density Hybrid SC-Parallel-Inductor Buck Converter with Reduced Inductor Current in 65nm CMOS. - Guigang Cai; Yan Lu 002; Rui Paulo Martins (ISSCC, 2022)

A 108nW 0.8mm2 Analog Voice Activity Detector (VAD) Featuring a Time-Domain CNN as a Programmable Feature Extractor and a Sparsity-Aware Computational Scheme in 28nm CMOS. - Feifei Chen; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (ISSCC, 2022)

A 4A 12-to-1 Flying Capacitor Cross-Connected DC-DC Converter with Inserted D>0.5 Control Achieving >2x Transient Inductor Current Slew Rate and 0.73× Theoretical Minimum Output Undershoot of DSD. - Tingxu Hu; Mo Huang; Yan Lu 002; Rui Paulo Martins (ISSCC, 2022)

A 266µW Bluetooth Low-Energy (BLE) Receiver Featuring an N-Path Passive Balun-LNA and a Pipeline Down-Mixing BB-Extraction Scheme Achieving 77dB SFDR and -3dBm OOB-B-1dB. - Haijun Shao; Pui-In Mak; Gengzhen Qi; Rui Paulo Martins (ISSCC, 2022)

Design Challenges and Considerations of Non-isolated Gate Driver for GaN-based Converters. - Xuchu Mu; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (MWSCAS, 2022)

A low dropout regulator with PSR under -48dB up to 20GHz for a SARADC reference buffer. - Yi Zeng; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (MWSCAS, 2022)

A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector. - Xinyi Ge; Yong Chen 005; Lin Wang 115; Nan Qi; Pui-In Mak; Rui Paulo Martins (NorCAS, 2022)

Modelling and Analysis of ΔΣ-Modulation-Based Output Spectrum Spur Reduction in Dual-Path Hybrid DC-DC Converters. - Xiongjie Zhang; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (PRIME, 2022)

Evaluation and Perspective of Analog Low-Dropout Voltage Regulators: A Review. - Tan Yee Chyan; Harikrishnan Ramiah; Sharifah Wan Muhamad Hatta; Nai Shyan Lai; Chee-Cheow Lim; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2022)

Low Voltage Switched-Capacitive-Based Reconfigurable Charge Pumps for Energy Harvesting Systems: An Overview. - Tian Siang Ho; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Yong Chen 005; Chee-Cheow Lim; Nai Shyan Lai; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2022)

Fully-Integrated Timers for Ultra-Low-Power Internet-of-Things Nodes - Fundamentals and Design Techniques. - Mikki How-Wen Loo; Harikrishnan Ramiah; Ka-Meng Lei; Chee-Cheow Lim; Nai Shyan Lai; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2022)

A 108-nW 0.8-mm2 Analog Voice Activity Detector Featuring a Time-Domain CNN With Sparsity-Aware Computation and Sparsified Quantization in 28-nm CMOS. - Feifei Chen; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

Arithmetic Progression Switched-Capacitor DC-DC Converter Topology With Soft VCR Transitions and Quasi-Symmetric Two-Phase Charge Delivery. - Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A Scalable High-Current High-Accuracy Dual-Loop Four-Phase Switching LDO for Microprocessors. - Xiangyu Mao; Yan Lu 002; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A Reconfigurable Single-Stage Asymmetrical Full-Wave Step-Down Rectifier for Bidirectional Device-to-Device Wireless Fast Charging. - Fangyu Mao; Yan Lu 002; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A 266-μW Bluetooth Low-Energy (BLE) Receiver Featuring an N-Path Passive Balun-LNA and a Pipeline Down-Mixing BB-Extraction Scheme Achieving 77-dB SFDR and -3-dBm OOB-B-1 dB. - Haijun Shao; Pui-In Mak; Gengzhen Qi; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A 1.7-3.6 GHz 20 MHz-Bandwidth Channel-Selection N-Path Passive-LNA Using a Switched-Capacitor-Transformer Network Achieving 23.5 dBm OB-IIP₃ and 3.4-4.8 dB NF. - Haijun Shao; Gengzhen Qi; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC With Code-Counter-Based Offset Calibration. - Hongshuai Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations. - Yanbo Zhang; Jin Zhang 034; Shubin Liu; Ruixue Ding; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS. - Xiaoteng Zhao; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS. - Xiaoteng Zhao; Yong Chen 005; Lin Wang 115; Pui-In Mak; Franco Maloberti; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier. - Zihao Zheng; Lai Wei; Jorge Lagos 001; Ewout Martens; Yan Zhu 001; Chi-Hang Chan; Jan Craninckx; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A Fully-Integrated Ambient RF Energy Harvesting System with 423-μW Output Power. - Kishore Kumar Pakkirisami Churchill; Harikrishnan Ramiah; Gabriel Chong; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (Sensors, 2022)

A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS. - Peng Chen 022; Xi Meng; Jun Yin 001; Pui-In Mak; Rui Paulo Martins; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS. - Peng Chen 022; Jun Yin 001; Feifei Zhang; Pui-In Mak; Rui Paulo Martins; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference. - Yu Duan; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Miniaturization of a Nuclear Magnetic Resonance System: Architecture and Design Considerations of Transceiver Integrated Circuits. - Shuhao Fan; Qi Zhou; Ka-Meng Lei; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Millimeter-Wave CMOS VCO Featuring a Mode-Ambiguity-Aware Multi-Resonant-RLCM Tank. - Hao Guo; Yong Chen 005; Chaowei Yang; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Capacitor-Cross-Connected Boost Converter With Duty Cycle < 0.5 Control for Extended Conversion-Ratio and Soft Start-Up. - Tingxu Hu; Mo Huang; Yan Lu 002; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Symmetrical Double Step-Down Converter With Extended Voltage Conversion Ratio. - Junwei Huang; Chi-Seng Lam; Yan Lu 002; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

An Entropy-Source-Preselection-Based Strong PUF With Strong Resilience to Machine Learning Attacks and High Energy Efficiency. - Jiahao Liu; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Weak PUF-Assisted Strong PUF With Inherent Immunity to Modeling Attacks and Ultra-Low BER. - Jiahao Liu; Yuanzhe Zhao; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 1.2-A Calibration-Free Hybrid LDO With In-Loop Quantization and Auxiliary Constant Current Control Achieving High Accuracy and Fast DVS. - Xiangyu Mao; Yan Lu 002; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Low-Power Multiband Blocker-Tolerant Receiver With a Steep Filtering Slope Using an N-Path LNA With Feedforward OB Blocker Cancellation and Filtering-by-Aliasing Baseband Amplifiers. - Haijun Shao; Gengzhen Qi; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Switched-Capacitor Bandgap Voltage Reference for IoT Applications. - Chi-Wa U; Man-Kay Law; Chi-Seng Lam; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Dual-Branch Series-Parallel Hybrid Buck DC-DC Converter With Flying Capacitor Voltage Auto-Balancing. - Chuang Wang 004; Yan Lu 002; Xiuping Li; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Highly Integrated Tri-Path Hybrid Buck Converter With Reduced Inductor Current and Self-Balanced Flying Capacitor Voltage. - Chuang Wang 004; Yan Lu 002; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Single-Opamp Third Order CT ΔΣ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp. - Kai Xing; Wei Wang 177; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 6-to-7.5-GHz 54-fsrms Jitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction. - Tailong Xu; Shenke Zhong; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 4T/Cell Amplifier-Chain-Based XOR PUF With Strong Machine Learning Attack Resilience. - Jieyun Zhang; Chongyao Xu; Man-Kay Law; Yang Jiang 002; Xiaojin Zhao; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

High-Performance Harmonic-Rich Single-Core VCO With Multi-LC Tank: A Tutorial. - Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review. - Mingqiang Guo; Sai-Weng Sin; Liang Qi 002; Dengke Xu; Guoxing Wang; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Miniaturized Energy Harvesting Systems Using Switched-Capacitor DC-DC Converters. - Man-Kay Law; Yang Jiang 002; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Wideband Continuous-Time MASH Delta-Sigma Modulators: A Tutorial Review. - Liang Qi 002; Yuekai Liu; Sai-Weng Sin; Xinpeng Xing; Guoxing Wang; Maurits Ortmanns; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

An Analog Multiplier Controlled Buck-Boost Converter. - Sibo Wen; Wen-Liang Zeng; Chi-Seng Lam; Franco Maloberti; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

An FPGA-Based Self-Reconfigurable Arc Fault Detection System for Smart Meters. - Ya-Jie Wu; Wai-Hei Choi; Chi-Seng Lam; Man-Chung Wong; Sai-Weng Sin; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

An FPGA-Based Energy-Efficient Reconfigurable Depthwise Separable Convolution Accelerator for Image Recognition. - Lei Xuan; Ka-Fai Un; Chi-Seng Lam; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 0.1-V VIN Subthreshold 3-Stage Dual-Branch Charge Pump With 43.4% Peak Power Conversion Efficiency Using Advanced Dynamic Gate-Bias. - Jack Kee Yong; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Gabriel Chong; Saad Mekhilef; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Reconfigurable CMOS Rectifier With 14-dB Power Dynamic Range Achieving >36-dB/mm2 FoM for RF-Based Hybrid Energy Harvesting. - Alexander Choo Chia Chun; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Yong Chen 005; Saad Mekhilef; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A -20-dBm Sensitivity RF Energy-Harvesting Rectifier Front End Using a Transformer IMN. - Wen Xun Lian; Harikrishnan Ramiah; Gabriel Chong; Kishore Kumar Pakkirisami Churchill; Nai Shyan Lai; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM. - Zunsong Yang; Yong Chen 005; Jia Yuan; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A 23-nA Quiescent Current Output-Capacitorless LDO Regulator for IoT Devices. - Shengnan Zhou; Xiangyu Mao; Cheng Huang 004; Rui Paulo Martins; Yan Lu 002 (ASICON, 2023)

A Cross-Coupled Hybrid SC Converter with Extended VCR Range and Intrinsic Loss Balance Achieving 90% Average Efficiency with 1.5% Variation Over Full Li-ion Battery Input Range and 0.95A/mm2 Peak Current Density. - Qiaobo Ma; Huihua Li; Xiongjie Zhang; Anyang Zhao; Yang Jiang 002; Man-Kay Law; Rui Paulo Martins; Pui-In Mak (A-SSCC, 2023)

Fully Integrated Reconfigurable Solar Energy Harvester for $100 mu mathrm{A}$ Burst Output Current Delivery with 78.6% Peak Energy Extraction Efficiency and Minimum Startup Incident Light Power of 0.27mW/cm2. - Jiangchao Wu; Guangshu Zhao; Litao Zhang; Yu Jia; Yang Jiang 002; Pui-In Mak; Rui Paulo Martins; Man Kay Law (A-SSCC, 2023)

Weightings in Incremental ADCs: A Tutorial Review. - Ruiqi Gao; Mingqiang Guo; Sai-Weng Sin; Liang Qi 002; Biao Wang; Guoxing Wang; Rui Paulo Martins (CICC, 2023)

A 5V-to-0.5V Inductor-First Inductor-on-Ground Switched Capacitor Multi-Path Hybrid DC-DC Converter. - Junwei Huang; Zhiguo Tong; Yan Lu 002; Chi-Seng Lam; Rui Paulo Martins (CICC, 2023)

A 12b 1GS/s ADC with Lightweight Input Buffer Distortion Background Calibration Achieving >75dB SFDR over PVT. - Xiang-Hui Pan; Buhui Rui; Yuefeng Cao; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (CICC, 2023)

An ELDC-Free 2.78mW 20MHz-BW 75.5dB-SNDR 4th- Order CTSDM Facilitated by 2nd-Order CT NS-SAR and AC-Coupled Negative-R. - ZiXuan Xu; Kai Xing; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (CICC, 2023)

A Double-Mode Sparse Compute-In-Memory Macro with Reconfigurable Single and Dual Layer Computation. - Yuanzhe Zhao; Minglei Zhang; Pengyu He; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (CICC, 2023)

Analog and Mixed-Signal CMOS Circuits: The emergence and leadership of a Lab, a reference Book and the future at the core of the A/D Interface in the IoE. - Rui Paulo Martins (ESSCIRC, 2023)

Simple-Logic Comparator-Offset Mitigation Technique for Resistor-Based Temperature Sensor in DFLL. - Dan Shi; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (ICTA, 2023)

A 9.97-GHz 190.6-dBc/Hz FOM CMOS VCO Featuring Nested Common-Mode Resonator and Intrinsic Differential 2nd-Harmonic Output. - Yunbo Huang; Yong Chen 005; Chaowei Yang; Pui-In Mak; Rui Paulo Martins (ISCAS, 2023)

A Compact 12V-to-1V 91.8% Peak Efficiency Hybrid Resonant Switched-Capacitor Parallel Inductor (ReSC-PL) Buck Converter. - Guigang Cai; Yan Lu 002; Rui Paulo Martins (ISSCC, 2023)

A Single-Channel 12b 2GS/s PVT-Robust Pipelined ADC with Critically Damped Ring Amplifier and Time-Domain Quantizer. - Yuefeng Cao; Minglei Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2023)

An 83.3-to-104.7GHz Harmonic-Extraction VCO Incorporating Multi-Resonance, Multi-Core, and Multi-Mode (3M) Techniques Achieving -124dBc/Hz Absolute PN and 190.7dBc/Hz $ text{FoM}_{ mathrm{T}}$. - Hao Guo; Yong Chen 005; Yunbo Huang; Pui-In Mak; Rui Paulo Martins (ISSCC, 2023)

A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness. - Junyan Hao; Minglei Zhang; Yanbo Zhang; Shubin Liu; Zhangming Zhu; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2023)

A 12V-to-1V Quad-Output Switched-Capacitor Buck Converter with Shared DC Capacitors Achieving 90.4% Peak Efficiency and 48mA/mm3 Power Density at 85% Efficiency. - Tingxu Hu; Mo Huang; Yan Lu 002; Rui Paulo Martins (ISSCC, 2023)

A 12/13.56MHz Crystal Oscillator with Binary-Search-Assisted Two-Step Injection Achieving 5.0nJ Startup Energy and 45.8μs Startup Time. - Haihua Li; Ka-Meng Lei; Pui-In Mak; Rui Paulo Martins (ISSCC, 2023)

A 47nW Mixed-Signal Voice Activity Detector (VAD) Featuring a Non-Volatile Capacitor-ROM, a Short-Time CNN Feature Extractor and an RNN Classifier. - Jinhai Lin; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (ISSCC, 2023)

A 42W Reconfigurable Bidirectional Power Delivery Voltage-Regulating Cable. - Zhiguo Tong; Junwei Huang; Yan Lu 002; Rui Paulo Martins (ISSCC, 2023)

A Continuously Scalable-Conversion-Ratio SC Converter with Reconfigurable VCF Step for High Efficiency over an Extended VCR Range. - Yuanfei Wang; Mo Huang; Yan Lu 002; Rui Paulo Martins (ISSCC, 2023)

A ULP Long-Range Active-RF Tag with Automatic Antenna-Interface Calibration Achieving 20.5% TX Efficiency at -22dBm EIRP, and -60.4dBm Sensitivity at 17.8nW RX Power. - Zhizhan Yang; Jun Yin 001; Wei-Han Yu; Haochen Zhang; Pui-In Mak; Rui Paulo Martins (ISSCC, 2023)

A 12V-lnput 1V-1.8V-Output 93.7% Peak Efficiency Dual-Inductor Quad-Path Hybrid DC-DC Converter. - Wen-Liang Zeng; Guigang Cai; Chon-Fai Lee; Chi-Seng Lam; Yan Lu 002; Sai-Weng Sin; Rui Paulo Martins (ISSCC, 2023)

A 22.4-to-26.8GHz Dual-Path-Synchronized Quad-Core Oscillator Achieving -138dBc/Hz PN and 193.3dBc/Hz FoM at 10MHz Offset from 25.8GHz. - Xiangxun Zhan; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (ISSCC, 2023)

A Single-Channel 70dB-SNDR 100MHz-BW 4th-Order Noise-Shaping Pipeline SAR ADC with Residue Amplifier Error Shaping. - Yanbo Zhang; Junyan Hao; Shubin Liu; Zhangming Zhu; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2023)

A 25MHz-BW 77.2dB-SNDR 2nd-Order Gain-Error-Shaping and NS Pipelined SAR ADC Based on a Quantization-Prediction-Unrolled Scheme. - Hongshuai Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2023)

A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input. - Hongzhi Zhao; Minglei Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2023)

A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors. - Minglei Zhang; Yuefeng Cao; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (VLSI Technology and Circuits, 2023)

A 0.05-to-3.1A 585mA/mm3 97.3%-Efficiency Outphase Switched-Capacitor Hybrid Buck Converter with Relieved Capacitor Inrush Current and COUT-Free Operation. - Xiongjie Zhang; Qiaobo Ma; Anyang Zhao; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (VLSI Technology and Circuits, 2023)

Design and Implementation of Hybrid DC-DC Converter: A Review. - Teck Seong Chang; Harikrishnan Ramiah; Yang Jiang 002; Chee-Cheow Lim; Nai Shyan Lai; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2023)

A Flexible Rooftop Photovoltaic-Inductive Wireless Power Transfer System for Low-Voltage DC Grid. - Io-Wa Iam; Zhaoyi Ding; Zhicong Huang; Chi-Seng Lam; Rui Paulo Martins; Pui-In Mak (IEEE Access, 2023)

Design Trends and Perspectives of Digital Low Dropout Voltage Regulators for Low Voltage Mobile Applications: A Review. - Li Fang Lai; Harikrishnan Ramiah; Tan Yee Chyan; Nai Shyan Lai; Chee-Cheow Lim; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2023)

High-Performance Multiband Ambient RF Energy Harvesting Front-End System for Sustainable IoT Applications - A Review. - Yi Chen Lee; Harikrishnan Ramiah; Alexander Choo Chia Chun; Kishore Kumar Pakkirisami Churchill; Nai Shyan Lai; Chee-Cheow Lim; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2023)

A Fully-Integrated CMOS Dual-Band RF Energy Harvesting Front-End Employing Adaptive Frequency Selection. - Wen Xun Lian; Harikrishnan Ramiah; Gabriel Chong; Kishore Kumar Pakkirisami Churchill; Nai Shyan Lai; Saad Mekhilef; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2023)

A Subthreshold Operation Series-Parallel Charge Pump Incorporating Dynamic Source-Fed Oscillator for Wide-Input-Voltage Energy Harvesting Application. - Jack Kee Yong; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Gabriel Chong; Saad Mekhilef; Nai Shyan Lai; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2023)

A 6.78-MHz Wireless Power Transfer System With Inherent Wireless Phase Shift Control Without Feedback Data Sensing Coil. - Xianglong Bai; Yan Lu 002; Chenchang Zhan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2023)

An SC-Parallel-Inductor Hybrid Buck Converter With Reduced Inductor Voltage and Current. - Guigang Cai; Yan Lu 002; Rui Paulo Martins (IEEE J. Solid State Circuits, 2023)

A Miniaturized 3-D-MRI Scanner Featuring an HV-SOI ASIC and Achieving a 10 × 8 × 8 mm3 Field of View. - Shuhao Fan; Qi Zhou; Ka-Meng Lei; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2023)

An Ultra-Low-Voltage Single-Crystal Oscillator-Timer (XO-Timer) Delivering 16-MHz and 32.258-kHz Clocks for Sub-0.5-V Energy-Harvesting BLE Radios in 28-nm CMOS. - Liwen Lin; Ka-Meng Lei; Pui-In Mak; Rui Paulo Martins (IEEE Open J. Circuits Syst., 2023)

A 27-dBm, 0.92-GHz CMOS Power Amplifier With Mode Switching and a High-Q Compact Inductor (HQCI) Achieving a 30% Back-Off PAE. - Arvind Singh Rawat; Jagadheswaran Rajendran; Selvakumar Mariappan; Narendra Kumar 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications. - Zhongyu Zhao; Rujian Cao; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Transfer-Path-Based Hardware-Reuse Strong PUF Achieving Modeling Attack Resilience With200 Million Training CRPs. - Chongyao Xu; Jieyun Zhang; Man-Kay Law; Xiaojin Zhao; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Inf. Forensics Secur., 2023)

IoT Cloud-Edge Reconfigurable Mixed-Signal Smart Meter Platform for Arc Fault Detection. - Ya-Jie Wu; Ricardo Brito; Wai-Hei Choi; Chi-Seng Lam; Man-Chung Wong; Sai-Weng Sin; Rui Paulo Martins (IEEE Internet Things J., 2023)

A Hybrid Single-Inductor Bipolar Triple-Output DC-DC Converter With High-Quality Positive Outputs for AMOLED Displays. - Fangyu Mao; Yan Lu 002; Franco Maloberti; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMSJitter, -258.7-dB FOM, and -75.17-dBc Reference Spur. - Yunbo Huang; Yong Chen 005; Bo Zhao 003; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMS Jitter, -260.2-dB FOM, and -70.96-dBc Reference Spur. - Yunbo Huang; Yong Chen 005; Bo Zhao 003; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Universal Stability Criterion for Type-I Sampling Phase-Locked Loops. - Yunbo Huang; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation. - Lin Wang 115; Yong Chen 005; Chaowei Yang; Xionghui Zhou; Mei Han; Paolo Stefano Crovetti; Pui-In Mak; Rui Paulo Martins (Int. J. Circuit Theory Appl., 2023)

A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique. - Lin Wang 115; Yong Chen 005; Chaowei Yang; Xiaoteng Zhao; Pui-In Mak; Franco Maloberti; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A High-Performance Dual-Topology CMOS Rectifier With 19.5-dB Power Dynamic Range for RF-Based Hybrid Energy Harvesting. - Alexander Choo Chia Chun; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Yong Chen 005; Saad Mekhilef; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Modeling-Attack-Resistant Strong PUF Exploiting Stagewise Obfuscated Interconnections With Improved Reliability. - Chongyao Xu; Litao Zhang; Man-Kay Law; Xiaojin Zhao; Pui-In Mak; Rui Paulo Martins (IEEE Internet Things J., 2023)

A 0.4-V 0.0294-mm2 Resistor-Based Temperature Sensor Achieving ±0.24 °C p2p Inaccuracy From40 °C to 125 °C and 385 fJ · K2 Resolution FoM in 65-nm CMOS. - Dan Shi; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2023)

Floating-Domain Integrated GaN Driver Techniques for DC-DC Converters: A Review. - Xuchu Mu; Guangshu Zhao; Anyang Zhao; Yang Jiang 002; Man-Kay Law; Makoto Takamiya; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 1-A Switching LDO With 40-mV Dropout Voltage and Fast DVS. - Xiangyu Mao; Yan Lu 002; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier. - Wenning Jiang; Yan Zhu 001; Chixiao Chen; Hao Xu 005; Qi Liu 010; Ming Liu 022; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2023)

A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time- Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward. - Shulin Zhao 004; Mingqiang Guo; Liang Qi 002; Dengke Xu; Guoxing Wang; Rui Paulo Martins; Sai-Weng Sin (IEEE J. Solid State Circuits, 2023)

A High-Current Scalable Parallel LDO Scheme With Analog-Digital Merged Control for Small Current-Sharing Mismatch. - Xiangyu Mao; Yan Lu 002; Chuang Wang 004; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 0.4-V 8400-μm2 Voltage Reference in 65-nm CMOS Exploiting Well-Proximity Effect. - Chengyu Che; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A High-PCE Range-Extension CMOS Rectifier Employing Advanced Topology Amalgamation Technique for Ambient RF Energy Harvesting. - Alexander Choo Chia Chun; Yi Chen Lee; Harikrishnan Ramiah; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 0.5V 22.5ppm/°C Bandgap Voltage Reference With Leakage Current Injection for Curvature Correction. - Chon-Fai Lee; Chi-Wa U; Rui Paulo Martins; Chi-Seng Lam (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 0.016mm2 Active Area 4GHz Fully Ring-Oscillator-Based Cascaded Fractional-N PLL With Burst-Mode Sampling. - Junlin Zhong; Xiaofeng Yang 004; Rui Paulo Martins; Yan Zhu 001; Chi-Hang Chan (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Reconfigurable CMOS Stack Rectifier With 22.8-dB Dynamic Range Achieving 47.91% Peak PCE for IoT/WSN Application. - Kishore Kumar Pakkirisami Churchill; Harikrishnan Ramiah; Alexander Choo Chia Chun; Gabriel Chong; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 12-to-1 Flying Capacitor Cross-Connected Buck Converter With Inserted D > 0.5 Control for Fast Transient Response. - Tingxu Hu; Mo Huang; Rui Paulo Martins; Yan Lu 002 (IEEE J. Solid State Circuits, 2023)

All Rivers Flow to the Sea: A High-Density Wireless Power Receiver With Split-Dual-Path and Hybrid-Quad-Path Step-Down Rectifying Conversion. - Zixiao Lin; Yan Lu 002; Fangyu Mao; Chuang Wang 004; Rui Paulo Martins (IEEE J. Solid State Circuits, 2023)

A 47-nW Voice Activity Detector (VAD) Featuring a Short-Time CNN Feature Extractor and an RNN-Based Classifier With a Non-Volatile CAP-ROM. - Jinhai Lin; Ka-Fai Un; Wei-Han Yu; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2023)

A 95% Peak Efficiency Modified KY Converter With Improved Flying Capacitor Charging in DCM for IoT Applications. - Caolei Pan; Wen-Liang Zeng; Chi-Seng Lam; Sai-Weng Sin; Chenchang Zhan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2023)

A Level Shifter With Almost Full Immunity to Positive dv/dt for Buck Converters. - Yunzhe Yang; Mo Huang; Sijun Du; Rui Paulo Martins; Yan Lu 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 28-nm 368-fJ/Cycle, 0.43%/V Supply-Sensitivity, FLL-Based RC Oscillator Featuring Positive-TC-Only Resistors and ΔΣM-Based Trimming. - Yunbo Huang; Yong Chen 005; Kaiyuan Yang 001; Paolo Crovetti; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Relative Stability Analysis of Multi-Loop Low Dropout Regulators Using a Sub-Loop Superposition Method. - Zihan Yang; Mo Huang; Yan Lu 002; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 12-to-1 V Quad-Output Switched-Capacitor Buck Converter With Shared DC Capacitors. - Tingxu Hu; Mo Huang; Rui Paulo Martins; Yan Lu 002 (IEEE J. Solid State Circuits, 2023)

A Second-Order NS Pipelined SAR ADC With Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator. - Hongshuai Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2023)

A 52.5-dB 2× Time-Interleaved 2.8-GS/s SAR ADC With 5-bit/Cycle Time-Domain Quantization and a Compact Signal DAC. - Hongzhi Zhao; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2023)

A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing. - Mingqiang Guo; Liang Qi 002; Weibing Zhao; Gang Xiao 001; Rui Paulo Martins; Sai-Weng Sin (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 10.5 W, 93% Efficient Dual-Path Hybrid (DPH)-Based DC-DC Converter Incorporating a Continuous-Current-Input Switched-Capacitor Stage and Enhanced IL Reduction for 12 V/24 V Inputs. - Qiaobo Ma; Xiongjie Zhang; Anyang Zhao; Huihua Li; Yang Jiang 002; Man-Kay Law; Makoto Takamiya; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion. - Xi Meng; Haoran Li; Peng Chen 022; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Continuous-Output-Current Buck-Boost Converter Without Right-Half-Plane-Zero (RHPZ). - Caolei Pan; Chenchang Zhan; Rui Paulo Martins; Chi-Seng Lam (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

An 1 V Supply, 740 nW, 8.7 ppm/°C Bandgap Voltage Reference With Segmented Curvature Compensation. - Chi-Wa U; Cong Liu; Rui Paulo Martins; Chi-Seng Lam (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration. - Lai Wei; Zihao Zheng; Nereo Markulic; Jorge Lagos 001; Ewout Martens; Rui Paulo Martins; Yan Zhu 001; Jan Craninckx; Chi-Hang Chan (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Fully Integrated CMOS Tri-Band Ambient RF Energy Harvesting System for IoT Devices. - Jack Kee Yong; Wen Xun Lian; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Gabriel Chong; Nai Shyan Lai; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 320MHz BW NS TD-ADC Assisted C/DT Hybrid Pipelined ADC with SAB-based Residue Amplifying Filter. - Kai Xing; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (A-SSCC, 2024)

A Miniaturized MRI Scanner Featuring a HighVoltage SOI ASIC for Non-Invasive Object Reconstruction and Flow Analysis. - Shuhao Fan; Qi Zhou; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (BioCAS, 2024)

The Race for the Extra Pico Second without Losing the Decibel: A Partial-Review of Single-Channel Energy-Efficient High-Speed Nyquist ADCs. - Chi-Hang Chan; Minglei Zhang; Yuefeng Cao; Honazhi Zhao; Rui Paulo Martins; Yan Zhu 001 (CICC, 2024)

A 1.58-nA CEPE-Based Hill-Climbing MPPT Technique with Compensated Ton Achieving 67.3% Efficiency at 10-nA Lload and > 97% MPPT Efficiency at VCR from 2 to 6. - Qiujin Chen; Tian Xia; Tingxu Hu; Yuanfei Wang; Mo Huang; Rui Paulo Martins; Yan Lu 002 (CICC, 2024)

A 75dB-SNDR 10MHz-BW 2-Channel Time-Interleaved Noise-Shaping SAR ADC Directly Powered by an On-Chip DC-DC Converter. - Haoyu Gong; Wen-Liang Zeng; Mingqiang Guo; Chi-Seng Lam; Shulin Zhao 004; Rui Paulo Martins; Sai-Weng Sin (CICC, 2024)

A 28nm 314.6TLFOPS/W Reconfigurable Floating-Point Analog Compute-In-Memory Macro with Exponent Approximation and Two-Stage Sharing TD-ADC. - Pengyu He; Yuanzhe Zhao; Heng Xie; Yang Wang 089; Shouyi Yin; Li Li 064; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan; Minglei Zhang (CICC, 2024)

A Fast-Slow Two-Module DC-DC Solution with Transient and Efficiency Improvements for 2.5D/3D Integration. - Junwei Huang; Zhiguo Tong; Xiangyu Mao; Chi-Seng Lam; Rui Paulo Martins; Yan Lu 002 (CICC, 2024)

A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering. - Ke Li; Xianyu Congzhou; Liang Qi 002; Mingqiang Guo; Rui Paulo Martins; Sai-Weng Sin (CICC, 2024)

A 96.7%-Efficient 2.5A Scalable DC-DC Converter Module with Complementary Dual-Mode Reconfigurable Hybrid Topology Achieving Always Inductor Current Reduction, Continuously Adjustable VCR Range, and Interleaving COUT Augmentation. - Huihua Li; Qiaobo Ma; Yang Jiang 002; Rui Paulo Martins; Pui-In Mak (CICC, 2024)

A Multi-Phase Multi-Path Hybrid Buck Converter for 9-48V to 0.8-1.2V Conversion with Improved DCR-Loss Reduction and Alleviated CFLY Current Gathering Achieving 88.3% Peak Efficiency and 176A/cm3Density. - Qiaobo Ma; Huihua Li; Jiahao Shi; Yang Jiang 002; Rui Paulo Martins; Pui-In Mak (CICC, 2024)

A Quad-Output Hybrid Buck Converter with 8-Inductor Helping One Spot from All Quarters for Multi-Core XPUs. - Xiangyu Mao; Junwei Huang; Zhiguo Tong; Rui Paulo Martins; Yan Lu 002 (CICC, 2024)

An Emulated Peak/Valley Curve Assisted Fast-Transient Buck Converter Achieving Precise One-Cycle Charge Balance with One-Parameter Calibration. - Zihao Tang; Mo Huang; Rui Paulo Martins; Yan Lu 002 (CICC, 2024)

A 0.25pJ/Comparison, 27.3μV Input Noise Dynamic Comparator Exploiting Stacked Floating Preamplifier with Cross-Coupled Feedback Inverters in 180nm CMOS. - Jiangchao Wu; Ke Hu; Xuanlin Chen; Pui-In Mak; Rui Paulo Martins; Man Kay Law (CICC, 2024)

A 12V-to-PoL CCC-Based Easy-Scalable Multiple-Phase Hybrid Converter with Auto VCF Balancing and Inactive CF Charging. - Jiacheng Yang; Tingxu Hu; Mo Huang; Rui Paulo Martins; Yan Lu 002 (CICC, 2024)

A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS. - Jian Yang; Tailong Xu; Xi Meng; Zhenghao Li; Jun Yin 001; Pui-In Mak; Rui Paulo Martins; Quan Pan 002 (CICC, 2024)

A PVT-Robust 8b 20GS/s Time-Interleaved SAR ADC with Quantization-Embedded Current-Mode Buffer and Differ-Based Dither Timing Skew Calibration. - Wei Zhang; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (CICC, 2024)

A 63ns Flipping Time, 93.6% Voltage Flipping Efficiency Auto-Calibrated Ultrasonic Energy Harvesting Interface from -25 to 85°C. - Guangshu Zhao; Chao Xie; Chenxi Wang; Yang Jiang 002; Milin Zhang 001; Pui-In Mak; Rui Paulo Martins; Man-Kay Law (CICC, 2024)

Invited Paper: A Multi-Phase Multi-Ratio Resonant Switched-Capacitor DC-DC Converter with Improved Power Density. - Jiyuan Liu; Qiaobo Ma; Yang Jiang 002; Rui Paulo Martins; Pui-In Mak (ICTA, 2024)

Invited Paper: A Ping-Pong Analog Delta Generator for Delt-Sigma Computing-In-Memory SRAM Macro for Edge AI Processing. - Ran Zhang; Ka-Fai Un; Zhensheng Li; Mingqiang Guo; Liang Qi 002; Rui Paulo Martins; Sai-Weng Sin (ICTA, 2024)

A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation. - Ran Zhang; Ka-Fai Un; Mingqiang Guo; Liang Qi 002; Dengke Xu; Weibing Zhao; Rui Paulo Martins; Franco Maloberti; Sai-Weng Sin (ISCAS, 2024)

Model Predictive Control with Fixed Switching Frequency for Thyristor-Controlled LC-Coupling Hybrid Active Power Filter. - Wai-Kit Sou; Rui Paulo Martins; Chi-Seng Lam (ISIE, 2024)

22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer. - Yuefeng Cao; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (ISSCC, 2024)

17.2 A Miniature Multi-Nuclei NMR/MRI Platform with a High-Voltage SOI ASIC Achieving a 134.4dB Image SNR with a 173×250×103μm3 Resolution. - Shuhao Fan; Qi Zhou; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

31.5 A 750mW, 37% Peak Efficiency Isolated DC-DC Converter with 54/18Mb/s Full-Duplex Communication Using a Single Pair of Transformers. - Tingxu Hu; Mo Huang; Rui Paulo Martins; Yan Lu 002 (ISSCC, 2024)

7.4 A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur. - Yunbo Huang; Yong Chen 005; Zunsong Yang; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment. - Haoran Li; Tailong Xu; Xi Meng; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

3.3 A 0.5V 6.14μW Trimming-Free Single-XO Dual-Output Frequency Reference with [5.1nJ, 120μs] XO Startup and [8.1nJ, 200μs] Successive-Approximation-Based RTC Calibration. - Rui Luo; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

28.3 A 12-28V to 0.6-1.8V Ratio-Regulatable Dickson SC Converter with Dual-Mode Phase Misalignment Operations Achieving 93.1% Efficiency and 6A Output. - Qiaobo Ma; Yang Jiang 002; Huihua Li; Xiongjie Zhang; Man-Kay Law; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

27.1 A Differential Hybrid Class-ED Power Amplifier with 27W Maximum Power and 82% Peak E2E Efficiency for Wireless Fast Charging To-Go. - Fangyu Mao; Rui Paulo Martins; Yan Lu 002 (ISSCC, 2024)

23.4 A 167 μW 71.7dB-SFDR 2.4GHz BLE Receiver Using a Passive Quadrature-Front-End, a Double-Sided Double-Balanced Cascaded Mixer and a Dual-Transformer-Coupled Class-D VCO. - Haijun Shao; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

17.9 A 1.8% FAR, 2ms Decision Latency, 1.73nJ/Decision Keywords Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-Domain Computing and Scalable 5T-SRAM. - Fei Tan; Wei-Han Yu; Jinhai Lin; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

31.6 A SIDO/DISO VCF-Step-Reconfigurable Continuously Scalable-Conversion-Ratio SC Converter Achieving 91.4%/92.6% Peak Efficiency and Almost-lossless Channel Switching. - Yuanfei Wang; Mo Huang; Rui Paulo Martins; Yan Lu 002 (ISSCC, 2024)

6.8 A 256×192-Pixel 30fps Automotive Direct Time-of-Flight LiDAR Using 8× Current-Integrating-Based TIA, Hybrid Pulse Position/Width Converter, and Intensity/CNN-Guided 3D Inpainting. - Chaorui Zou; Yaozhong Ou; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan; Minglei Zhang (ISSCC, 2024)

A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial Sum Boosting and Analog Non-Uniform Quantization. - Guoqiang Xin; Fei Tan; Junde Li; Junren Chen; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (MWSCAS, 2024)

A Fully Integrated 48-V GaN Driver Using Parallel-Multistep-Series Reconfigurable Switched-Capacitor Bank Achieving 7.7nC/mm2 On-Chip Bootstrap Driving Density. - Xuchu Mu; Yang Jiang 002; Rui Paulo Martins; Pui-In Mak (VLSI Technology and Circuits, 2024)

A Fast Startup 38.4-MHz Crystal Oscillator Achieving 99-nJ Startup Energy With Adaptive Chirping. - Abdolraouf Rahmani; Harikrishnan Ramiah; Ka-Meng Lei; Chee-Cheow Lim; Nai Shyan Lai; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2024)

A Constant-Power and Optimal-Transfer-Efficiency Wireless Inductive Power Transfer Converter for Battery Charger. - Io-Wa Iam; Chio-Kuan Choi; Chi-Seng Lam; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Ind. Electron., 2024)

Fully Symmetrical Obfuscated Interconnection and Weak-PUF-Assisted Challenge Obfuscation Strong PUFs Against Machine-Learning Modeling Attacks. - Chongyao Xu; Litao Zhang; Pui-In Mak; Rui Paulo Martins; Man-Kay Law (IEEE Trans. Inf. Forensics Secur., 2024)

One-Cycle-Startup Relaxation Oscillator Using Ratiometric Threshold-Referenced and Self-Synchronized Power Gating Techniques. - Guangshu Zhao; Zhiming Xiao; Pui-In Mak; Rui Paulo Martins; Man-Kay Law (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 12-/13.56-MHz Crystal Oscillator With Binary-Search-Assisted Two-Step Injection Achieving 5.0-nJ Startup Energy and 45.8-μs Startup Time. - Haihua Li; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A 0.05-mm2 2.91-nJ/Decision Keyword-Spotting (KWS) Chip Featuring an Always-Retention 5T-SRAM in 28-nm CMOS. - Fei Tan; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

Sub-μW Auto-Calibration Bandgap Voltage Reference With 1σ Inaccuracy of ± 0.12% Within - 40°C to 120°C. - Chi-Wa U; Man-Kay Law; Rui Paulo Martins; Chi-Seng Lam (IEEE J. Solid State Circuits, 2024)

A Radio-Frequency Cross-Connected Rectifier With LC Source Degeneration. - Qiujin Chen; Mo Huang; Tian Xia; Jun Yin 001; Haiwen Liu; Rui Paulo Martins; Yan Lu 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R. - ZiXuan Xu; Kai Xing; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2024)

Extended Power Dynamic Range and Enhanced Power Conversion Efficiency of a Switched-Capacitor DC-DC Converter: A Tutorial. - Tian Siang Ho; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

An Outphase-Interleaved Switched-Capacitor Hybrid Buck Converter With Relieved Capacitor Inrush Current and COUT-Free Operations. - Xiongjie Zhang; Qiaobo Ma; Yang Jiang 002; Anyang Zhao; Man-Kay Law; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A 12V-to-1V Outphase-Interleaved SC Hybrid Converter With Enhanced Inductor De-Energizing Slew Rate and Adaptive Deadtime Control. - Xiongjie Zhang; Xinman Li; Anyang Zhao; Yang Jiang 002; Weihang Zhang; Jincheng Zhang; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 93.4% Peak Efficiency CLOAD-Free Multi-Phase Switched-Capacitor DC-DC Converter Achieving a Fast DVS up to 222.5 mV/ns. - Feiyu Li; Qishen Fang; Jiangchao Wu; Yang Jiang 002; Pui-In Mak; Rui Paulo Martins; Man-Kay Law (IEEE J. Solid State Circuits, 2024)

A Fully Synthesizable All-Digital Dual-Loop Distributed Low-Dropout Regulator. - Xiangyu Mao; Yan Lu 002; Rui Paulo Martins (IEEE J. Solid State Circuits, 2024)

A Single-Inductor Multiple-Output DC-DC Converter With Fixed-Frequency Victim-Last Charge Control for Reduced Cross Regulation. - Yang Li 219; Mo Huang; Rui Paulo Martins; Yan Lu 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 0.013 mm² 3.2-ns Input Range 10-Bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65-nm CMOS. - Xin Lu; Jiangchao Wu; Zhao Wang; Yifei Xiang; Liyuan Liu; Pui-In Mak; Rui Paulo Martins; Man-Kay Law (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

FLEX-CIM: A Flexible Kernel Size 1-GHz 181.6-TOPS/W 25.63-TOPS/mm2 Analog Compute-in-Memory Macro. - Yuzhao Fu; Wei-Han Yu; Ka-Fai Un; Chi-Hang Chan; Yan Zhu 001; Minglei Zhang; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A 24-V-Input Highly Integrated Interleaved-Inductor Multiple Step-Down Hybrid DC-DC Converter With Inherent Current Equalization Characteristics. - Xiongjie Zhang; Anyang Zhao; Qiaobo Ma; Yang Jiang 002; Man-Kay Law; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A Cross-Coupled Hybrid Switched-Capacitor Buck Converter With Extended Conversion Range and Enhanced DCR Loss Reduction. - Qiaobo Ma; Huihua Li; Xiongjie Zhang; Anyang Zhao; Yang Jiang 002; Man-Kay Law; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

Miniature Magnetic Resonance Imaging System for in situ Monitoring of Bacterial Growth and Biofilm Formation. - Qi Zhou; Shuhao Fan; Ka-Meng Lei; Donhee Ham; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Biomed. Circuits Syst., 2024)

A Complementary Drain-Grounded VCO-PA Improving Transmit Efficiency Over a Wide EIRP Range. - Zhizhan Yang; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A ULP Long-Range Active-RF Tag With Automatically Calibrated Antenna-TRX Interface. - Zhizhan Yang; Jun Yin 001; Wei-Han Yu; Haochen Zhang; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A 28-nm 18.7 TOPS/mm² 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh. - Yi Zhan; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A 256 × 192 -Pixel Direct Time-of-Flight LiDAR Receiver With a Current-Integrating-Based AFE Supporting 240-m-Range Imaging. - Chaorui Zou; Yaozhong Ou; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan; Minglei Zhang (IEEE J. Solid State Circuits, 2024)

CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization. - Yuzhao Fu; Jixuan Li; Wei-Han Yu; Ka-Fai Un; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

0.4-V Supply, 12-nW Reverse Bandgap Voltage Reference With Single BJT and Indirect Curvature Compensation. - Chon-Fai Lee; Chi-Wa U; Rui Paulo Martins; Chi-Seng Lam (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications. - Rujian Cao; Zhongyu Zhao; Ka-Fai Un; Wei-Han Yu; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 512-nW 0.003-mm² Forward-Forward Closed Box Trainer for an Analog Voice Activity Detector in 28-nm CMOS. - Junde Li; Guoqiang Xin; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 0.012-mm2 0.244-pJ/bit successive approximation register analog-to-digital converter-based true random number generator for Internet of Things applications in a 65-nm complementary metal-oxide-semiconductor. - Kai Cheng; Yong Chen 005; Paolo Stefano Crovetti; Rui Paulo Martins; Pui-In Mak (Int. J. Circuit Theory Appl., 2024)

A 12-GS/s 12-b 4× Time-Interleaved ADC Using Input-Independent Timing Skew Calibration With Global Dither Injection and Linearized Input Buffer. - Yuefeng Cao; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2024)

A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment. - Haoran Li; Tailong Xu; Xi Meng; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A 167- μW 71.7-dB SFDR 2.4-GHz BLE Receiver Using a Passive Quadrature Front End, a Double- Sided Double-Balanced Cascaded Mixer, and a Dual-Transformer-Coupled Class-D VCO. - Haijun Shao; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

Revealing Hybrid DC-DC Converters - Mo Huang; Rui Paulo Martins (Springer, 2025)

Fully-Integrated Low-Dropout Regulators - Xiangyu Mao; Yan Lu 002; Rui Paulo Martins (Springer, 2025)

A 22.4-25.6GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage and Balanced 2nd Harmonic Extraction Achieving 45.8fsrms Jitter and -254.3dB FoM. - Yunbo Huang; Zunsong Yang; Hongyu Ren; Rui Paulo Martins; Yan Lu 002; Nan Sun 001; Nan Qi; Yong Chen 005 (CICC, 2025)

A 12.5GS/s 14.7mW 4×TI Pipelined Hybrid TD-SAR ADC with Residual Time-Voltage Amplification. - Haoyu Li; Boyang Wang; Hongjiang Chen; Sai-Weng Sin; Yutao Peng; Xizhu Peng; He Tang; Chao Fan; Liang Qi 002; Rui Paulo Martins; Mingqiang Guo (CICC, 2025)

A 48x OSR 105.4-dB SNDR 24-kHz BW CT Zoom ADC with Reset Tri-level DWA and On-chip Negative-R Calibration. - Yuyu Lin; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (CICC, 2025)

A 30-110V Resonant Buck-Boost Power-Bus Charger Achieving 50-A Peak Laser-Current Pulse Generation in 2ns for MHz-Frequency Automotive LiDAR Transmitter. - Hangxiao Ma; Qiaobo Ma; Xuchu Mu; Yang Jiang 002; Rui Paulo Martins; Pui-In Mak (CICC, 2025)

A Fast-transient Buck Converter with One-Cycle-Balancing Control for Single and Consecutive Load Steps. - Zihao Tang; Rui Paulo Martins; Mo Huang (CICC, 2025)

An SC-first Hybrid SCVR with 4xCF Continuously Scalable-Conversion Ratio SC Achieving 92.5% Peak Efficiency. - Yuanfei Wang; Zhiyuan Zhang; Ziyang Zhong; Yihan Zhang; Rui Paulo Martins; Mo Huang (CICC, 2025)

A 300-kHz 3-Level Flyback Converter Achieving 93% Peak Efficiency and 50% Reduction in Transformer Size. - Yuanzhuo Wu; Rui Paulo Martins; Mo Huang (CICC, 2025)

25-nA Modified Hybrid Ladder Converter with Efficient Output-Capacitor Charge Recycling and 90% Battery Lifetime Extension. - Jianxin Yang; Rui Paulo Martins; Mo Huang (CICC, 2025)

A 98.5% Peak Efficiency 2/3-Phase Buck-or-Boost Converter With VCR-Independent Loss Optimization and Unconditional RHP Zero Elimination Achieving 2.76A/mm2-Current-Density and 6.5µs Recovery. - Xiongjie Zhang; Xinman Li; Yang Jiang 002; Zhangming Zhu; Rui Paulo Martins; Pui-In Mak (CICC, 2025)

A 28nm Value-Wise Hybrid-Domain Compute-in-Memory Macro with Heterogeneous Memory Fabric and Asynchronous Sparsity Manager. - Yuanzhe Zhao; Yang Wang 089; Yuheng Wang; Heng Xie; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan; Shouyi Yin; Minglei Zhang (CICC, 2025)

A Reconfigurable 0.69-1.02nJ/Classification Biomedical AI Processor for Intelligent Health Monitoring Devices. - Yuanzhe Zhao; Yuheng Wang; Zijian Wang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan; Minglei Zhang (CICC, 2025)

A Keyword-Spotting(KWS) Chip Featuring a Bio-Inspired Neuron Model in 65-nm CMOS. - Yantong Liu; Fei Tan; Ka-Fai Un; Wei-Han Yu; Rui Paulo Martins; Pui-In Mak (CNIOT, 2025)

A 4-Phase Adaptive On-Time Controlled Buck Converter With Auto-Synchronized Dynamic Frequency and Transient-Enhancement Techniques. - Zhiming He; Sai-Weng Sin; Rui Paulo Martins; Yan Lu 002 (ISCAS, 2025)

A 5V-to-0.8V Inductor-First 2L2C Multi-Path Hybrid DC-DC Converter. - Yasi Hu; Junwei Huang; Chi-Seng Lam; Mo Huang; Rui Paulo Martins; Yan Lu 002 (ISCAS, 2025)

A 12V-Input 1.8V-0.8V-Output Multiple-Output Hybrid Buck DC-DC Converter with a Shared Flying Capacitor. - Fucong Luo; Junwei Huang; Mo Huang; Rui Paulo Martins; Yan Lu 002 (ISCAS, 2025)

A 0.6V Digital-intensive Pulse Injection 32-kHz Crystal Oscillator Using Stacked Logic Gates. - Zhizhan Yang; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (ISCAS, 2025)

An Always Dual-Path Hybrid DC-DC Converter with Multiphase Interleaving Switched-Capacitor Cell Obtaining 45% Output Ripple Reduction. - Zhewen Yu; Junwei Huang; Zhiguo Tong; Mo Huang; Rui Paulo Martins; Yan Lu 002 (ISCAS, 2025)

A Chip-based Miniature MRI Platform with Integrated PDMS-PCB Coil Frontend for Microlitre-volume Sample Analysis. - Qi Zhou; Shuhao Fan; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (ISCAS, 2025)

A PVT-Robust 5.5GHz Fractional-N Cascaded RO-Based Digital PLL with Voltage-Domain Feedforward Noise Cancellation. - Yu Duan; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (ISSCC, 2025)

31.4 A 91.25% Peak Power-Conversion-Efficiency Capacitive Power-Management IC Supporting up to 5.68mJ Burst Energy Delivery Using a Single External Capacitor for mm-Scale IoT Applications. - Qishen Fang; Feiyu Li; Rui Paulo Martins; Man-Kay Law (ISSCC, 2025)

21.9 A 20MHz & 1MHz Dual-Loop Non-Uniform-Multi-Inductor Hybrid DC-DC Converter with Specified Inductor Current Allocation and Fast Transient Response. - Junwei Huang; Xiangyu Mao; Zhiguo Tong; Zhewen Yu; Wenjie Yang; Chi-Seng Lam; Rui Paulo Martins; Yan Lu 002 (ISSCC, 2025)

19.7 A 27GHz Fractional-N Sub-Sampling PLL Achieving 57.9fsrms Jitter, -249.7dB FoM, and 1.98µS Locking Time Using Polarity-Reversible SSPD. - Haoran Li; Jinge Li; Xueying Jiang; Xi Meng; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (ISSCC, 2025)

24.4 A 10b 3GS/s Time-Domain ADC with Mutually Exclusive Metastability Correction and Wide Common-Mode Input. - Zijian Liu; Minglei Zhang; Wei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (ISSCC, 2025)

27.5: A 4, 100µm2 Wire-Metal-Based Temperature Sensor with a Fractional-Discharge FLL and a Time-Domain Amplifier with ±0.2°C Inaccuracy (3σ) from -40 to 125°C and 45fJ·K2 Resolution FoM in 28nm CMOS. - Dan Shi; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (ISSCC, 2025)

An 85-to-230VAC to 3.3-to-4.6VDc 1.52W Capacitor-Drop Sigma-Floating-SC AC-DC Converter with 81.3% Peak Efficiency. - Fei Song; Shousheng Han; Rui Paulo Martins; Yan Lu 002 (ISSCC, 2025)

HOOP: A Scalable Hybrid DC-DC Converter Ring for High-Performance Computing. - Zhiguo Tong; Zhewen Yu; Junwei Huang; Xiangyu Mao; Bernhard Wicht; Rui Paulo Martins; Yan Lu 002 (ISSCC, 2025)

32.1 A 180MHz 45.3%-Peak-Efficiency Isolated Converter Using Q-Downsize Class-D Power Amplifier with Inherent Shoot-Through Current Blocking and High Tolerance for Efficiency Despite Frequency Misalignments. - Tian Xia; Qiujin Chen; Shujing Wang 012; Rui Paulo Martins; Mo Huang (ISSCC, 2025)

21.3 A Segmented-Interlacing Multi-Phase Hybrid Converter with Inherently Auto-Balanced ILs and Boosted IL Slew Rate During Load Transients. - Jiacheng Yang; Rui Paulo Martins; Mo Huang (ISSCC, 2025)

A Bi-Directional Dual-Path Boost-48V-Buck Hybrid Converter for High-Voltage Power-Transmission Cable in Light-Weight Humanoid Robots. - Wenjie Yang; Zhiguo Tong; Junwei Huang; Rui Paulo Martins; Yan Lu 002 (ISSCC, 2025)

A 94.8nW Battery-Free Intelligent Silicon Platform Enabling Distributed, Adaptive, and Event-Driven Multimodal Sensing at the Edge. - Haochen Zhang; Wei-Han Yu; Zhongyu Zhao; Zhizhan Yang; Ka-Fai Un; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (ISSCC, 2025)

24.5 A 72GS/s 9b Time-Interleaved Pipeline-SAR ADC Achieving 55.3/49.3dB SFDR at 20GHz/Nyquist Inputs in 16nm FinFET. - Yannan Zhang; Minglei Zhang; Zehang Wu; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (ISSCC, 2025)

24.3: A PVT-Robust 2× Interleaved 2.2GS/s ADC with Gated-CCRO-Based Quantizer Shared Across Channels and Steps Achieving >4.5GHz ERBW. - Junlin Zhong; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (ISSCC, 2025)

On the Usage of Genetic Algorithms, Reinforcement Learning and Bayesian Optimisation for RF IC Design Automation. - Margarida Lourenço; Bingbing Zhao; Junde Li; Marcelino B. Santos; Pui-In Mak; Rui Paulo Martins; Wei-Han Yu; Fábio Passos (SMACD, 2025)

A 90.7-nW Vibration-Based Condition Monitoring Chip Featuring a Digital Compute-in-Memory- Based DNN Accelerator Using an Ultra-Low-Power 13T-SRAM Cell. - Haochen Zhang; Wei-Han Yu; Zhizhan Yang; Ka-Fai Un; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2025)

A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer. - Yuefeng Cao; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2025)

A Double Pulse Overlapping Laser Diode Driver With Minimum 100-ps Pulse for LiDAR System. - Zhiguo Tong; Junwei Huang; Xiangyu Mao; Rui Paulo Martins; Yan Lu 002 (IEEE J. Solid State Circuits, 2025)

A VCF-Step-Reconfigurable Continuously Scalable-Conversion-Ratio Switched- Capacitor Converter. - Yuanfei Wang; Mo Huang; Qiujin Chen; Rui Paulo Martins; Yan Lu 002 (IEEE J. Solid State Circuits, 2025)

A Series-LC-Assisted Oscillator Achieving -140.2 dBc/Hz Phase Noise and 187.5 dBc/Hz FoM at 10 MHz Offset From 10.7 GHz. - Xiangxun Zhan; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

Area-efficient ultra-wide-tuning-range ring oscillators in 65-nm complementary metal-oxide-semiconductor. - Chaowei Yang; Yong Chen 005; Kai Cheng; Paolo Stefano Crovetti; Rui Paulo Martins; Pui-In Mak (Int. J. Circuit Theory Appl., 2025)

An Isolated DC-DC Converter With Full-Duplex Communication Using a Single Pair of Transformers. - Tingxu Hu; Yan Lu 002; Rui Paulo Martins; Mo Huang (IEEE J. Solid State Circuits, 2025)

A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined ΔΣ ADC With DAC Image Prefiltering. - Ke Li; Haoyu Gong; Xianyu Congzhou; Zhensheng Li; Liang Qi 002; Mingqiang Guo; Rui Paulo Martins; Sai-Weng Sin (IEEE J. Solid State Circuits, 2025)

A 1.8% FAR, 2 ms Decision Latency, 1.73 nJ/Decision Keywords-Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-IF-Domain Computing and Scalable 5T-SRAM. - Fei Tan; Wei-Han Yu; Jinhai Lin; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2025)

An 840-to-970 MHz Multimodal Wake-Up Receiver With a Q-Equalized Antenna-ED Interface and 2-Dimensional Wake-Up Identification. - Zhizhan Yang; Haochen Zhang; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 0.35-0.5-V 0.0136-mm² 12 -MHz Digital Frequency-Locked Loop With 1.06%/V Line Sensitivity in 65-nm CMOS. - Dan Shi; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction. - Tailong Xu; Haoran Li; Xi Meng; Xiangxun Zhan; Yatao Peng; Jun Yin 001; Shiheng Yang; Chao Fan; Zhixiang Huang; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A 0.5-V 6.14- μW Trimming-Free Single-XO Dual-Output Frequency Reference With [5.1-nJ, 120- μs] XO Start-Up and [8.1-nJ, 200- μs] Successive-Approximation-Based RTC Calibration. - Rui Luo; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2025)

A Systematic Review of Voltage Reference Circuits: Spanning Room Temperature to Cryogenic Applications. - Chen Deng; Sai Wu; Chengcheng Liu; Yatao Peng; Man-Kay Law; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

GSLP-CIM: A 28-nm Globally Systolic and Locally Parallel CNN/Transformer Accelerator With Scalable and Reconfigurable eDRAM Compute-in-Memory Macro for Flexible Dataflow. - Yi Zhan; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Resonant Switched-Capacitor Parallel Inductor Hybrid Buck Converter. - Guigang Cai; Rui Paulo Martins; Yan Lu 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Single-XO Dual-Output Frequency Reference Featuring Adaptive RTC Calibration Achieving 0.63 ppm/°C Temperature Coefficient From -40 °C to 125 °C. - Rui Luo; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A 28-nm MFCC-Free Keyword Switchable Keyword Spotting (KWS) System With Transferred Training Algorithm. - Fei Tan; Yujia Wang; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A Capacitorless Flipped-Voltage-Follower-Based Low-Dropout Regulator Incorporating Adaptive-Compensation Buffer. - Tan Yee Chyan; Harikrishnan Ramiah; Sharifah Wan Muhamad Hatta; Chee-Cheow Lim; Rui Paulo Martins; Pui-In Mak; Yong Chen 005 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Miniature Multinuclei NMR/MRI Platform With a High-Voltage SOI ASIC. - Shuhao Fan; Qi Zhou; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2025)

A Multi-Path Inductor-First Inductor-on-Ground Switched-Capacitor Hybrid DC-DC Converter. - Junwei Huang; Zhiguo Tong; Chi-Seng Lam; Xiangyu Mao; Rui Paulo Martins; Yan Lu 002 (IEEE J. Solid State Circuits, 2025)

An Intrinsically PVT Robust 10-bit 2.6-GS/s Dynamic Pipelined ADC With Dual-Path Time-Assisted Residue Generation Scheme. - Junyan Hao; Minglei Zhang; Zijian Liu; Yanbo Zhang; Shubin Liu; Zhangming Zhu; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2025)

A 362-TOPS/W Mixed-Signal MAC Macro With Sampling-Weight-Nonlinearity Cancellation and Dynamic-Amplified Accumulation. - Ran Zhang; Xueru Cen; Ka-Fai Un; Mingqiang Guo; Liang Qi 002; Rui Paulo Martins; Sai-Weng Sin (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Single-Input RF Energy-Harvesting Interface With Compensated-CEPE Control and 3-D Hill-Climbing MPPT Achieving -28.5-dBm Sensitivity. - Qiujin Chen; Tian Xia; Tingxu Hu; Yuanfei Wang; Yan Lu 002; Rui Paulo Martins; Mo Huang (IEEE J. Solid State Circuits, 2025)

An 800-MHz 8.17-TOPS/W 0.63-TOPS/mm2 Memory-Utilization-Aware CNN Accelerator Featuring a Memory Stationary Dataflow. - Jixuan Li; Ke Li; Ka-Fai Un; Wei-Han Yu; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2025)

A Bidirectional USB Power Delivery Voltage-Regulating Cable. - Zhiguo Tong; Junwei Huang; Xiangyu Mao; Rui Paulo Martins; Yan Lu 002 (IEEE J. Solid State Circuits, 2025)

A 97.8 GOPS/W FPGA-Based Residual-Block-Aware CNN Accelerator Featuring Multi-Clock PW2 Pipeline and Adaptive-Resolution Quantization. - Jixuan Li; Ke Li; Ka-Fai Un; Wei-Han Yu; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

An Emulated Curve Assisted Fast-Transient Buck Converter With One-Cycle Charge Balance. - Zihao Tang; Yan Lu 002; Rui Paulo Martins; Mo Huang (IEEE J. Solid State Circuits, 2025)

A Dual-Inductor Quad-Path Hybrid Buck (2L4PHB) Converter With Reduced Inductor Current. - Wen-Liang Zeng; Guigang Cai; Yan Lu 002; Sai-Weng Sin; Rui Paulo Martins; Chi-Seng Lam (IEEE J. Solid State Circuits, 2025)

Design and Analysis of a Type-II Sampling PLL With Automatic Frequency and Phase Calibrations Achieving 0.62-μs Locking Time. - Jian Yang; Tailong Xu; Xi Meng; Zhenghao Li; Jun Yin 001; Rui Paulo Martins; Pui-In Mak; Quan Pan 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)