Multiplier-based double precision floating point divider according to the IEEE-754 standard. - Vítor Silva; Rui Policarpo Duarte; Mário P. Véstias; Horácio C. Neto (ARC, 2008)

Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs. - Rui Policarpo Duarte; Horácio C. Neto; Mário P. Véstias (DSD, 2009)

High-level linear projection circuit design optimization framework for FPGAs under over-clocking. - Rui Policarpo Duarte; Christos-Savvas Bouganis (FPL, 2012)

A Unified Framework for Over-Clocking Linear Projections on FPGAs under PVT Variation. - Rui Policarpo Duarte; Christos-Savvas Bouganis (ARC, 2014)

Pushing the performance boundary of linear projection designs through device specific optimisations (abstract only). - Rui Policarpo Duarte; Christos-Savvas Bouganis (FPGA, 2014)

Over-clocking of Linear Projection Designs through Device Specific Optimisations. - Rui Policarpo Duarte; Christos-Savvas Bouganis (IPDPS Workshops, 2014)

Zero-latency datapath error correction framework for over-clocking DSP applications on FPGAs. - Rui Policarpo Duarte; Christos-Savvas Bouganis (ReConFig, 2014)

Enhancing stochastic computations via process variation. - Rui Policarpo Duarte; Mário P. Véstias; Horácio C. Neto (FPL, 2015)

CardioWheel: ECG Biometrics on the Steering Wheel. - André Lourenço; Ana Priscila Alves; Carlos Carreiras; Rui Policarpo Duarte; Ana L. N. Fred (ECML/PKDD (3), 2015)

Designing Hardware/Software Systems for Embedded High-Performance Computing. - Mário P. Véstias; Rui Policarpo Duarte; Horácio C. Neto (CoRR, 2015)

ARC 2014 Over-Clocking KLT Designs on FPGAs under Process, Voltage, and Temperature Variation. - Rui Policarpo Duarte; Christos-Savvas Bouganis (ACM Trans. Reconfigurable Technol. Syst., 2015)

XtokaxtikoX: A stochastic computing-based autonomous cyber-physical system. - Rui Policarpo Duarte; Horácio C. Neto; Mário P. Véstias (ICRC, 2016)

Variation-Aware Optimisation for Reconfigurable Cyber-Physical Systems. - Rui Policarpo Duarte; Christos-Savvas Bouganis (DoCEIS, 2016)

A hybrid ASIC/FPGA fault-tolerant artificial pancreas. - Michail S. Vavouras; Rui Policarpo Duarte; Antonino Armato; Christos-Savvas Bouganis (SAMOS, 2016)

Parallel dot-products for deep learning on FPGA. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (FPL, 2017)

Transport Protocols for Large Bandwidth-Delay Product Networks - TCP Extensions and Alternative Transport Protocols. - Rui Policarpo Duarte (CoRR, 2017)

Making data center computations fast, but not so furious. - Daniel Porto 002; João Loff; Rui Policarpo Duarte; Luis Ceze; Rodrigo Rodrigues 001 (CoRR, 2017)

Stochastic Processors on FPGAs to Compute Sensor Data Towards Fault-Tolerant IoT Systems. - Rui Policarpo Duarte; Horácio C. Neto (DSC, 2018)

Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (FPL, 2018)

FPGA-based OpenCL Accelerator for Discovering Temporal Patterns in Gene Expression Data Using Biclustering. - Rui Policarpo Duarte; Álvaro Simões; Rui Henriques; Horácio C. Neto (PBio@EuroMPI, 2018)

Fault-Tolerant Architecture for On-board Dual-Core Synthetic-Aperture Radar Imaging. - Helena Cruz; Rui Policarpo Duarte; Horácio C. Neto (ARC, 2019)

Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (FPL, 2019)

Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores. - Luís Fiolhais; Fernando M. Gonçalves; Rui Policarpo Duarte; Mário P. Véstias; José T. de Sousa (ISCAS, 2019)

kNN-STUFF: kNN STreaming Unit for Fpgas. - João Vieira; Rui Policarpo Duarte; Horácio C. Neto (IEEE Access, 2019)

Embedded Fault-Tolerant Accelerator Architecture for Synthetic-Aperture Radar Backprojection. - Helena Cruz; Rui Policarpo Duarte; Horácio C. Neto (J. Aerosp. Inf. Syst., 2019)

Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection Algorithm. - Rui Policarpo Duarte; Helena Cruz; Horácio C. Neto (ARC, 2020)

A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (IEEE Access, 2020)

Moving Deep Learning to the Edge. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (Algorithms, 2020)

A fast and scalable architecture to run convolutional neural networks in low density FPGAs. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (Microprocess. Microsystems, 2020)

A Full Featured Configurable Accelerator for Object Detection With YOLO. - Daniel Pestana; Pedro R. Miranda; João D. Lopes; Rui Policarpo Duarte; Mário P. Véstias; Horácio C. Neto; José T. de Sousa (IEEE Access, 2021)

Configurable Hardware Core for IoT Object Detection. - Pedro R. Miranda; Daniel Pestana; João D. Lopes; Rui Policarpo Duarte; Mário P. Véstias; Horácio C. Neto; José T. de Sousa (Future Internet, 2021)

A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective. - Helena Cruz; Mário P. Véstias; José Monteiro 001; Horácio C. Neto; Rui Policarpo Duarte (Remote. Sens., 2022)

Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA. - David Mota; Helena Cruz; Pedro R. Miranda; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto; Mário P. Véstias (IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2022)

Energy-Efficient and Real-Time Wearable for Wellbeing-Monitoring IoT System Based on SoC-FPGA. - Maria Inês Frutuoso; Horácio C. Neto; Mário P. Véstias; Rui Policarpo Duarte (Algorithms, 2023)

Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units. - Mário P. Véstias; Rui Policarpo Duarte; José T. de Sousa; Horácio C. Neto (ACM Trans. Reconfigurable Technol. Syst., 2023)