A power-optimized reconfigurable CT ΔΣ modulator in 65nm CMOS. - Rui Wang 035; Xiaoke Wen; Kamran Azadet; Changzhi Li; Jinghong Chen (ISCAS, 2012)

A 12b 60MS/s SHA-less opamp-sharing pipeline A/D with switch-embedded dual input OTAs. - Xiaoke Wen; Rui Wang 035; Renguo Peng; Min Hao; Jinghong Chen (ISCAS, 2012)

A 30mW 10b 250MS/s dual channel SHA-less pipeline ADC in 0.18µm CMOS. - Xiaoke Wen; Rui Wang 035; Siyu Yang; Lei Chen; Jinghong Chen (MWSCAS, 2012)

A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS. - Yang You; Sudipto Chakraborty; Rui Wang 035; Jinghong Chen (A-SSCC, 2015)

A 150 MHz bandwidth continuous-time ΔΣ modulator in 28 nm CMOS with DAC calibration. - Rui Wang 035; Yang You; Guoying Wu; Xiaoke Wen; Tianshi He; Jinghong Chen; Kamran Azadet; Ping Gui (MWSCAS, 2015)

A 180-Vpp Integrated Linear Amplifier for Ultrasonic Imaging Applications in a High-Voltage CMOS SOI Technology. - Kexu Sun; Zheng Gao; Ping Gui; Rui Wang 035; Ismail Oguzman; Xiaochen Xu; Karthik Vasanth; Qifa Zhou; K. Kirk Shung (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Effect of OPAMP Input Offset on Continuous-Time ΔΣ Modulators With Current-Mode DACs. - Rui Wang 035; Deping Huang; Tianshi He; Jinghong Chen; Yang You; Ping Gui (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 1-16 Gb/s All-Digital Clock and Data Recovery With a Wideband High-Linearity Phase Interpolator. - Guoying Wu; Deping Huang; Jingxiao Li; Ping Gui; Tianwei Liu; Shita Guo; Rui Wang 035; Yanli Fan; Sudipto Chakraborty; Mark Morgan (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Temperature Compensated Triple-Path PLL With KVCO Non-Linearity Desensitization Capable of Operating at 77 K. - Tianwei Liu; Xiaoran Wang; Rui Wang 035; Guoying Wu; Tao Zhang 034; Ping Gui (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)